Datenblatt-pdf.com


EP1C4 Schematic ( PDF Datasheet ) - Altera Corporation

Teilenummer EP1C4
Beschreibung Cyclone FPGA Family
Hersteller Altera Corporation
Logo Altera Corporation Logo 




Gesamt 30 Seiten
EP1C4 Datasheet, Funktion
www.DataSheet.co.kr
March 2003, ver. 1.1
®
Cyclone
FPGA Family
Data Sheet
Introduction
Preliminary
Information
Features...
The CycloneTM field programmable gate array family is based on a 1.5-V,
0.13-µm, all-layer copper SRAM process, with densities up to 20,060 logic
elements (LEs) and up to 288 Kbits of RAM. With features like phase-
locked loops (PLLs) for clocking and a dedicated double data rate (DDR)
interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory
requirements, Cyclone devices are a cost-effective solution for data-path
applications. Cyclone devices support various I/O standards, including
LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz,
32-bit peripheral component interconnect (PCI), for interfacing with and
supporting ASSP and ASIC devices. Altera also offers new low-cost serial
configuration devices to configure Cyclone devices.
2,910 to 20,060 LEs, see Table 1
Up to 294,912 RAM bits (36,864 bytes)
Supports configuration through low-cost serial configuration device
Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
Support for 66-MHz, 32-bit PCI standard
Low speed (311 Mbps) LVDS I/O support
Up to two PLLs per device provide clock multiplication and phase
shifting
Up to eight global clock lines with six clock resources available per
logic array block (LAB) row
Support for external memory, including DDR SDRAM (133 MHz),
FCRAM, and single data rate (SDR) SDRAM
Support for multiple intellectual property (IP) cores, including
AlteraMegaCorefunctions and Altera Megafunctions Partners
Program (AMPPSM) megafunctions
Table 1. Cyclone Device Features
Feature
EP1C3
LEs
M4K RAM blocks (128 × 36 bits)
Total RAM bits
PLLs
Maximum user I/O pins (1)
2,910
13
59,904
1
104
Note to Table 1:
(1) This parameter includes global clock pins.
EP1C4
4,000
17
78,336
2
301
EP1C6
5,980
20
92,160
2
185
EP1C12
12,060
52
239,616
2
249
EP1C20
20,060
64
294,912
2
301
Altera Corporation
DS-CYCLONE-1.1
1
Datasheet pdf - http://www.DataSheet4U.net/






EP1C4 Datasheet, Funktion
www.DataSheet.co.kr
Cyclone FPGA Family Data Sheet
Preliminary Information
Logic Array
Blocks
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local
interconnect, look-up table (LUT) chain, and register chain connection
lines. The local interconnect transfers signals between LEs in the same
LAB. LUT chain connections transfer the output of one LE’s LUT to the
adjacent LE for fast sequential LUT connections within the same LAB.
Register chain connections transfer the output of one LE’s register to the
adjacent LE’s register within an LAB. The Quartus® II Compiler places
associated logic within an LAB or adjacent LABs, allowing the use of local,
LUT chain, and register chain connections for performance and area
efficiency. Figure 2 details the Cyclone LAB.
Figure 2. Cyclone LAB Structure
Row Interconnect
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
LAB Local Interconnect
Column Interconnect
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
6 Altera Corporation
Datasheet pdf - http://www.DataSheet4U.net/

6 Page









EP1C4 pdf, datenblatt
www.DataSheet.co.kr
Cyclone FPGA Family Data Sheet
Preliminary Information
Normal Mode
The normal mode is suitable for general logic applications and
combinatorial functions. In normal mode, four data inputs from the LAB
local interconnect are inputs to a four-input LUT (see Figure 6). The
Quartus II Compiler automatically selects the carry-in or the data3 signal
as one of the inputs to the LUT. Each LE can use LUT chain connections to
drive its combinatorial output directly to the next LE in the LAB.
Asynchronous load data for the register comes from the data3 input of
the LE. LEs in normal mode support packed registers.
Figure 6. LE in Normal Mode
sload
sclear
(LAB Wide) (LAB Wide)
Register chain
connection
aload
(LAB Wide)
addnsub (LAB Wide)
(1)
data1
data2
data3
cin (from cout
of previous LE)
data4
4-Input
LUT
clock (LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
ALD/PRE
ADATA Q
D
ENA
CLRN
Row, column, and
direct link routing
Row, column, and
direct link routing
Local routing
LUT chain
connection
Register Feedback
Register
chain output
Note to Figure 6:
(1) This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain.
12
Altera Corporation
Datasheet pdf - http://www.DataSheet4U.net/

12 Page





SeitenGesamt 30 Seiten
PDF Download[ EP1C4 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
EP1C12Cyclone FPGA FamilyAltera Corporation
Altera Corporation
EP1C12QxxxCyclone FPGA FamilyAltera Corporation
Altera Corporation
EP1C12TCyclone FPGA FamilyAltera
Altera
EP1C12TxxxxCyclone FPGA FamilyAltera
Altera
EP1C20Cyclone FPGA FamilyAltera Corporation
Altera Corporation

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche