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PDF D720200 Data sheet ( Hoja de datos )
| Número de pieza | D720200 | |
| Descripción | UPD720200 | |
| Fabricantes | NEC | |
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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
PD720200
USB 3.0 HOST CONTROLLER
The PD720200 is the Universal Serial Bus 3.0 host controller, which complies with Universal Serial Bus 3.0
Specification, and Intel’s eXtensible Host Controller Interface (xHCI).
The PD720200 has PCI Express® bus interface, and it is applicable for PCI Express solution for host PC system.
The PD720200 works up to 5 Gbps for data transfer when connecting to USB 3.0 compliant peripherals, while
maintaining compatibility with existing USB peripheral devices.
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.
PD720200 User’s Manual : TBD
FEATURES
Compliant with Universal Serial Bus 3.0 specification
Revision 1.0, which is released by USB
Implementers Forum, Inc
- Supports the following speed data rate as
follows;
Low-speed (1.5 Mbps) / Full-speed (12 Mbps) /
High-speed (480 Mbps) / Super-speed (5 Gbps)
- Supports 2 downstream ports for all speeds
- Supports all USB compliant data transfer type as
follows; Control / Bulk / Interrupt / Isochronous
transfer
Compliant with Intel’s eXtensible Host Controller
Interface (xHCI) Specification revision 0.95
Support USB legacy function
Compliant with PCI Express® Base Specification 2.0
Supports ExpressCardTM Standard Release1.0
Supports PCI Express® Card Electromechanical
Specification Revision 2.0
Supports PCI Bus Power Management Interface
Specification revision 1.2
Operational registers are direct-mapped to PCI
memory space
Supports Serial Peripheral Interface (SPI) type ROM
System clock: 24 MHz crystal or 48MHz external
clock.
3.3 V and 1.05 V power supply
ORDERING INFORMATION
Part Number
PD720200F1-DAK-A
Package
176-pin plastic FBGA (10 10)
Remark
Lead-free product
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC
Electronics Corporation. The information in this document is subject to change without notice. Before using this document,
please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an
NEC Electronics sales representative for availability and additional information.
Document No. ISG-YD1-000127-05
Date Published April , 2009 CP (N)
2009
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
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PD720200
System clock
Pin Name
XT1
Ball No.
N14
XT2 M14
CSEL
P6
Direction Buffer Type Active Level
Function
I OSC
－ Oscillator in
During 24 MHz crystal mode, connect to 24 MHz crystal.
In using external 48 MHz clock, this pin must be clamped
to low.
I/O OSC
－ Oscillator out or external clock input
During 24 MHz crystal mode, connect to 24 MHz crystal.
In using external 48 MHz clock, this pin is used for
external 48 MHz clock input signal..
I 3.3V Input
－ Clock select signal
0: 24 MHz crystal mode
1: 48 MHz external clock input
System Interface signal
Pin Name
PONRSTB
Ball No.
P5
SMIB
H1
Direction Buffer Type Active Level
Function
I 3.3V
Schmitt
Input
O 3.3V
Output
(6mA)
Low Power on reset signal. When supporting wakeup from
D3cold, this signal should be pulled high with system
auxiliary power supply.
Low System management Interrupt signal “SMI#”.
Preliminary Data Sheet
5
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5 Page 
www.DataSheet.co.kr
PD720200
AC Characteristics (VDD33 = 3.3V 10%, VDD10 = 1.05V 5%, TA = 0 to 85C)
System clock (XT1/XT2) ratings
Parameter
Symbol
Condition
Min. Typ. Max. Units
Clock frequency
FCLK
Crystal
100
24
100
MHz
ppm ppm
Oscillator block
100
48
100
MHz
ppm ppm
Clock duty cycle
TDUTY
40 50 60
%
Remarks 1. Required accuracy of crystal or oscillator block is including initial frequency accuracy, the spread of
Crystal capacitor loading, supply voltage, temperature and aging, etc.
Power on Reset (PONRSTB) Timings
Parameter
Symbol
Condition
Min. Max. Units
Power on reset time
TPONRST
Figure 2-1
1 ms
Remarks 1. There is no order to power-on of VDD33, U2AVDD33, U3AVDD33 and VDD10.
2. All power sources should be stable within 100ms from the fastest rising edge of power sources.
3. PONRSTB shall be de-asserted after all power sources and the system clock become stable.
PCI Express Interface - Reference Clock (PECLKP and PECLKN) Timings
Parameter
Symbol
Condition
Rising Edge Rate
Falling Edge Rate
Differential Input High Voltage
TRISE
TFALL
VIH
Figure 2-5
Figure 2-5
Figure 2-8
Differential Input Low Voltage
VIL Figure 2-8
Absolute crossing point voltage
VCROSS
Figure 2-3
Variation of VCROSS over all rising clock edge
VCROSS DELTA
Figure 2-4
Ring-back Voltage Margin
VRB Figure 2-8
Time before VRB is allowed
Average Clock Period Accuracy
TSTABLE
TPERIOD AVG
Figure 2-8
Absolute Period (including Jitter and Spread
Spectrum)
TPERIOD ABS
Cycle to Cycle Jitter
VCCJITTER
Absolute Max input voltage
VMAX
Figure 2-3
Absolute Min input voltage
VMIN\
Figure 2-3
Duty Cycle
Rising edge rate (PECLKP) to falling edge rate
(PECLKN) matching
Clock source DC impedance
ZC-DC
Figure 2-2
Min.
0.6
0.6
150
250
100
500
300
9.847
Max.
4.0
4.0
150
550
140
100
2800
10.203
Units
V/ns
V/ns
mV
mV
mV
mV
mV
ps
ppm
ps
150 ps
1.15
V
0.3 V
40 60 %
20 %
40 60
Preliminary Data Sheet
11
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| PDF Descargar | [ Datasheet D720200.PDF ] | |
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