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PDF DS10CP154A Data sheet ( Hoja de datos )
| Número de pieza | DS10CP154A | |
| Descripción | 1.5 Gbps 4x4 LVDS Crosspoint Switch | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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January 23, 2009
DS10CP154A
1.5 Gbps 4x4 LVDS Crosspoint Switch
General Description
The DS10CP154A is a 1.5 Gbps 4x4 LVDS crosspoint switch
optimized for high-speed signal routing and switching over
FR-4 printed circuit board backplanes and balanced cables.
Fully differential signal paths ensure exceptional signal in-
tegrity and noise immunity. The non-blocking architecture
allows connections of any input to any output or outputs. The
switch configuration can be accomplished via external pins or
the System Management Bus (SMBus) interface. In addition,
the SMBus circuitry enables the loss of signal (LOS) monitors
that can inform a system of the presence of an open inputs
condition (e.g. disconnected cable).
Wide input common mode range allows the switch to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires a minimal
space on the board while the flow-through pinout allows easy
board layout. Each differential input and output is internally
terminated with a 100Ω resistor to lower return losses, reduce
component count and further minimize board space.
Features
■ DC - 1.5 Gbps low jitter, low skew, low power operation
■ Pin and SMBus configurable, fully differential, non-
blocking architecture
■ Wide input common mode range enables DC coupled
interface to CML or LVPECL drivers
■ LOS circuitry detects open inputs fault condition
■ On-chip 100 Ω input and output termination minimizes
insertion and return losses, reduces component count and
minimizes board space
■ 8 kV ESD on LVDS I/O pins protects adjoining
components
■ Small 6 mm x 6 mm LLP-40 space saving package
Applications
■ High-speed channel select applications
■ Clock and data buffering and muxing
■ SD / HD SDI Routers
Typical Application
© 2009 National Semiconductor Corporation 300737
30073703
www.national.com
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Absolute Maximum Ratings (Note 4)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
−0.3V to +4V
LVCMOS Input Voltage
LVCMOS Output Voltage
LVDS Input Voltage
−0.3V to (VCC + 0.3V)
−0.3V to (VCC + 0.3V)
−0.3V to +4V
LVDS Differential Input Voltage
0V to 1.0V
LVDS Output Voltage
LVDS Differential Output Voltage
−0.3V to (VCC + 0.3V)
0V to 1.0V
LVDS Output Short Circuit Current
Duration
5 ms
Junction Temperature
+150°C
Storage Temperature Range
−65°C to +150°C
Lead Temperature Range
Soldering (4 sec.)
+260°C
Maximum Package Power Dissipation at 25°C
SQA Package
4.65W
Derate SQA Package
37.2 mW/°C above +25°C
Package Thermal Resistance
θJA
θJC
ESD Susceptibility
HBM (Note 1)
MM (Note 2)
CDM (Note 3)
+26.9°C/W
+3.8°C/W
≥8 kV
≥250V
≥1250V
Note 1: Human Body Model, applicable std. JESD22-A114C
Note 2: Machine Model, applicable std. JESD22-A115-A
Note 3: Field Induced Charge Device Model, applicable std.
JESD22-C101-C
Recommended Operating
Conditions
Min Typ Max
Supply Voltage (VCC)
3.0 3.3 3.6
Receiver Differential Input 0
1.0
Voltage (VID)
Operating Free Air
−40 +25 +85
Temperature (TA)
SMBus (SDA, SCL)
3.6
Units
V
V
°C
V
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 6, 7)
Symbol
Parameter
Conditions
Min
LVCMOS DC SPECIFICATIONS
VIH High Level Input Voltage
VIL Low Level Input Voltage
IIH High Level Input Current
VIN = 3.6V
VCC = 3.6V
EN_smb pin
2.0
GND
40
IIL Low Level Input Current
VCL Input Clamp Voltage
VOL Low Level Output Voltage
LVDS INPUT DC SPECIFICATIONS
VIN = GND
VCC = 3.6V
ICL = −18 mA, VCC = 0V
IOL= 4 mA
SDA pin
VID
VTH
VTL
VCMR
Input Differential Voltage
Differential Input High Threshold
Differential Input Low Threshold
Common Mode Voltage Range
VCM = +0.05V or VCC-0.05V
VID = 100 mV
0
−100
0.05
Typ
0
175
0
−0.9
0
0
IIN Input Current
CIN Input Capacitance
RIN Input Termination Resistor
VIN = 3.6V or 0V
VCC = 3.6V or 0V
Any LVDS Input Pin to GND
Between IN+ and IN-
±1
1.7
100
Max
VDD
0.8
±10
250
±10
−1.5
0.4
1
+100
VCC -
0.05
±10
Units
V
V
μA
μA
μA
V
V
V
mV
mV
V
μA
pF
Ω
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TABLE 3. Input Select Pins Configuration for the Output OUT2
S21 S20 INPUT SELECTED
0 0 IN0
0 1 IN1
1 0 IN2
1 1 IN3
TABLE 4. Input Select Pins Configuration for the Output OUT3
S31 S30 INPUT SELECTED
0 0 IN0
0 1 IN1
1 0 IN2
1 1 IN3
DS10CP154A OPERATION IN THE SMBUS MODE
The DS10CP154A operates as a slave on the System Man-
agement Bus (SMBus) when the EN_smb pin is set to a high
(1). Under these conditions, the SCL pin is a clock input while
the SDA pin is a serial data input pin.
slave address are hard wired inside the DS10CP154A and
are “101”. The four least significant bits of the address are
assigned to pins ADDR3-ADDR0 and are set by connecting
these pins to GND for a low (0) or to VCC for a high (1). The
complete slave address is shown in the following table:
Device Address
Based on the SMBus 2.0 specification, the DS10CP154A has
a 7-bit slave address. The three most significant bits of the
TABLE 5. DS10CP154A Slave Address
1
MSB
0
1
ADDR3
ADDR2
ADDR1
ADDR0
LSB
This slave address configuration allows up to sixteen
DS10CP154A devices on a single SMBus bus.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable dur-
ing the time when SCK is high.
There are three unique states for the SMBus:
START: A HIGH to LOW transition on SDA while SCK is high
indicates a message START condition.
STOP: A LOW to HIGH transition on SDA while SCK is high
indicates a message STOP condition.
IDLE: If SCK and SDA are both high for a time exceeding
tBUF from the last detected STOP condition or if they are high
for a total exceeding the maximum specification for tHIGH
then the bus will transfer to the IDLE state.
SMBus Transactions
A transaction begins with the host placing the DS10CP154A
SMBus into the START condition, then a byte (8 bits) is trans-
ferred, MSB first, followed by a ninth ACK bit. ACK bits are ‘0’
to signify an ACK, or ‘1’ to signify NACK, after this the host
holds the SCL line low, and waits for the receiver to raise the
SDA line as an ACKnowledge that the byte has been re-
ceived.
Writing to a Register
To write a register, the following protocol is used (see SMBus
2.0 specification):
1) The Host drives a START condition, the 7-bit SMBus ad-
dress, and a “0” indicating a WRITE.
2) The Device (Slave) drives an ACK bit (“0”).
3) The Host drives the 8-bit Register Address.
4) The Device drives an ACK bit (“0”).
5) The Host drives the 8-bit data byte.
6) The Device drives an ACK bit “0”.
7) The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes Idle and
communication with other SMBus devices may now occur.
Reading From a Register
To read a register, the following protocol is used (see SMBus
2.0 specification):
1) The Host drives a START condition, the 7-bit SMBus ad-
dress, and a “0” indicating a WRITE.
2) The Device (Slave) drives an ACK bit (“0”).
3) The Host drives the 8-bit Register Address.
4) The Device drives an ACK bit (“0”).
5) The Host drives a START condition.
6) The Host drives the 7-bit SMBus Address, and a “1” indi-
cating a READ.
7) The Device drives an ACK bit “0”.
8) The Device drives the 8-bit data value (register contents).
9) The Host drives a NACK bit “1” indicating end of READ
transfer.
10) The Host drives a STOP condition.
The READ transaction is completed, the bus goes Idle and
communication with other SMBus devices may now occur.
11
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