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PDF W9425G6DH Data sheet ( Hoja de datos )
| Número de pieza | W9425G6DH | |
| Descripción | 4M X 4 BANKS X 16 BITS DDR SDRAM | |
| Fabricantes | Winbond | |
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W9425G6DH
4M × 4 BANKS × 16 BITS DDR SDRAM
Table of Contents-
1. GENERAL DESCRIPTION............................................................................................................. 4
2. FEATURES .................................................................................................................................... 4
3. KEY PARAMETERS ...................................................................................................................... 5
4. PIN CONFIGURATION .................................................................................................................. 6
5. PIN DESCRIPTION........................................................................................................................ 7
6. BLOCK DIAGRAM ......................................................................................................................... 8
7. FUNCTIONAL DESCRIPTION....................................................................................................... 9
7.1 Power Up Sequence............................................................................................................ 9
7.2 Command Function ............................................................................................................. 9
7.2.1 Bank Activate Command ........................................................................................................9
7.2.2 Bank Precharge Command ....................................................................................................9
7.2.3 Precharge All Command ........................................................................................................9
7.2.4 Write Command .....................................................................................................................9
7.2.5 Write with Auto-precharge Command...................................................................................10
7.2.6 Read Command ...................................................................................................................10
7.2.7 Read with Auto-precharge Command ..................................................................................10
7.2.8 Mode Register Set Command ..............................................................................................10
7.2.9 Extended Mode Register Set Command ..............................................................................10
7.2.10 No-Operation Command ......................................................................................................10
7.2.11 Burst Read Stop Command..................................................................................................11
7.2.12 Device Deselect Command ..................................................................................................11
7.2.13 Auto Refresh Command .......................................................................................................11
7.2.14 Self Refresh Entry Command...............................................................................................11
7.2.15 Self Refresh Exit Command .................................................................................................11
7.2.16 Data Write Enable /Disable Command .................................................................................12
7.3 Read Operation ................................................................................................................. 12
7.4 Write Operation ................................................................................................................. 12
7.5 Precharge .......................................................................................................................... 13
7.6 Burst Termination .............................................................................................................. 13
7.7 Refresh Operation ............................................................................................................. 13
7.8 Power Down Mode ............................................................................................................ 13
7.9 Input Clock Frequency Change during Precharge Power Down Mode ............................ 14
7.10 Mode Register Operation .................................................................................................. 14
7.10.1 Burst Length field (A2 to A0) ................................................................................................14
Publication Release Date:Nov. 20, 2007
- 1 - Revision A7
1 page  
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W9425G6DH
3. KEY PARAMETERS
SYMBOL
tCK
tRAS
tRC
IDD0
IDD1
IDD4R
IDD4W
IDD5
IDD6
DESCRIPTION
CL = 2
Clock Cycle Time
CL = 2.5
CL = 3
Active to Precharge Command Period
Active to Ref/Active Command Period
Operating Current:
One Bank Active-Precharge
Operating Current:
One Bank Active-Read-Precharge
Burst Operation Read Current
Burst Operation Write Current
Auto Refresh Current
Self Refresh Current
MIN./MAX.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Min.
Max.
Max.
Max.
Max.
Max.
Max.
-4
-
-
-
-
4 nS
10 nS
36 nS
52 nS
110 mA
150 mA
190 mA
190 mA
190 mA
5 mA
-5
7.5 nS
10 nS
6 nS
10 nS
5 nS
10 nS
40 nS
55 nS
110 mA
150 mA
180 mA
180 mA
190 mA
3 mA
-6/-6I
7.5 nS
12 nS
6 nS
12 nS
6 nS
12 nS
42 nS
60 nS
110 mA
150 mA
170 mA
170 mA
190 mA
3 mA
-75/75I
7.5 nS
12 nS
7.5 nS
12 nS
7.5 nS
12 nS
45 nS
67.5 nS
110 mA
150 mA
160 mA
160 mA
190 mA
3 mA
Publication Release Date:Nov. 20, 2007
- 5 - Revision A7
5 Page 
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W9425G6DH
7.2.11 Burst Read Stop Command
( RAS = "H", CAS = "H", WE = "L")
The Burst stop command is used to stop the burst operation. This command is only valid during a
Burst Read operation.
7.2.12 Device Deselect Command
( CS = "H")
The Device Deselect command disables the command decoder so that the RAS , CAS ,
WE and Address inputs are ignored. This command is similar to the No-Operation command.
7.2.13 Auto Refresh Command
( RAS = "L", CAS = "L", WE = "H", CKE = "H", BS0, BS1, A0 to A12 = Don’t Care)
AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS–
BEFORE–RAS (CBR) refresh in previous DRAM types. This command is non persistent, so it
must be issued each time a refresh is required. The refresh addressing is generated by the
internal refresh controller. This makes the address bits ”Don’t Care” during an AUTO REFRESH
command. The DDR SDRAM requires AUTO REFRESH cycles at an average periodic interval of
tREFI (maximum). To allow for improved efficiency in scheduling and switching between tasks,
some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH
commands can be posted to any given DDR SDRAM, and the maximum absolute interval
between any AUTO REFRESH command and the next AUTO REFRESH command is 8 * tREFI.
7.2.14 Self Refresh Entry Command
( RAS = "L", CAS = "L", WE = "H", CKE = "L", BS0, BS1, A0 to A12 = Don’t Care)
The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of
the system is powered down. When in the self refresh mode, the DDR SDRAM retains data
without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH
command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF
REFRESH, and is automatically enabled upon exiting SELF REFRESH. Any time the DLL is
enabled a DLL Reset must follow and 200 clock cycles should occur before a READ command
can be issued. Input signals except CKE are “Don’t Care” during SELF REFRESH. Since CKE is
an SSTL_2 input, VREF must be maintained during SELF REFRESH.
7.2.15 Self Refresh Exit Command
(CKE = "H", CS = "H" or CKE = "H", RAS = "H", CAS = "H")
The procedure for exiting self refresh requires a sequence of commands. First, CLK must be
stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP
commands issued for tXSNR because time is required for the completion of any internal refresh in
progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for
200 clock cycles before applying any other command.
The use of SELF REFREH mode introduces the possibility that an internally timed event can be
missed when CKE is raised for exit from self refresh mode. Upon exit from SELF REFRESH an
extra auto refresh command is recommended.
- 11 -
Publication Release Date:Nov. 20, 2007
Revision A7
11 Page | ||
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