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PE12016G Schematic ( PDF Datasheet ) - Productivity Engineering

Teilenummer PE12016G
Beschreibung (PE12016G / PE12024G) Incremental Encoder
Hersteller Productivity Engineering
Logo Productivity Engineering Logo 




Gesamt 25 Seiten
PE12016G Datasheet, Funktion
www.DataSheet4U.net
PE12016G / PE12024G
December 15, 2005 Version 1.7
Incremental Encoder
Features:
Functional and pincompatible with obsolete
TI CF32007NW/NT / THCT12016 /
THCT 12024 / LS2000
5 V and 3.3 V Operation
0.6u CMOS Process
Direction discriminator
Pulse width measurement
Frequency measurement
Cascadable (PE12016G only)
TTL compatible
8 Bit parallel tristateable Bus
Simple read & write procedure
High speed 20 MHz clock operation
PE12016G ONLY: 1:1 Replacement for
LS2000AN
PE12024G ONLY: 24-Bit resolution,
separate UA0 counter reset
WEEE & RoHS Compliant according
DIRECTIVE 2002/95/EC
(Green Package Material)
PE12016G
PDIP28-600 Mil
1
CS
28
VCC
RD UP
D0 DOWN
D1 WE
D2 RESET
D3 A0
GND
CLK
D4 UA2
D5 UA1
D6 M0
D7 M1
BORROW
M2
CARRY READY
GND KLI-KLO
14 15
PE12024G
PDIP24-300 Mil
1 24
CS VCC
RD UA0
D0 A1
D1 WE
D2 RESET
D3 A0
GND CLK
D4 UA2
D5 UA1
D6 M0
D7 M1
GND
12
M2
13
Description:
The PE12016G/12024G INCREMENTAL
ENCODER INTERFACE can independently
determine the direction or displacement of a
mechanical device or axis based on two input
signals from transducers in quadrature.
Alternatively, it can measure a pulse width using
a known clock rate, or a frequency, by counting
input pulses over a
known time interval. It includes one 16-bit or 24-
bit counter which may also be used separately
(PE12016G only). The PE12016G may be
cascaded to provide accuracy greater than 16-
bits. Both devices are designed for use in many
microprocessor-based systems.
December 15, 2005 (Version 1.7)
Seite 1 / 25
PE12016G/24G






PE12016G Datasheet, Funktion
www.DataSheet4U.net
December 15, 2005 Version 1.7
PE12016G / PE12024G
Incremental Encoder
Mode 1-5 : Direction Discriminator Modes
The quadrature signals Ua1 and Ua2 identify
forward or backward directions. If Ua1 leads
Ua2, the forward direction is indicated and the
counter
will count up; if Ua1 lags Ua2, the reverse
direction is indicated and the counter will count
down.
Fig. 3: Direction Discriminator Modes
Both Ua1 and Ua2 are stored on the clock falling
edge in the first of a pair of consecutive D-type
flip-flops, and are transferred to the next on the
clock rising edge. By comparing the states of the
four flip-flops and checking the mode inputs, the
up or down count pulses are generated; see
Figures 4 and 5.
Fig. 4: Direction Discriminator Up Clock
December 15, 2005 (Version 1.7)
Seite 6 / 25
PE12016G/24G

6 Page









PE12016G pdf, datenblatt
www.DataSheet4U.net
December 15, 2005 Version 1.7
Pin Description - continued
Pin Name Pin Number
PDIP28 PDIP24
PE12016G PE12024G
Ua0 - 23
CLK 22 18
/A0 23 19
/A1
/RESET
-
24
22
20
/WE 25 21
/DOWN
26
-
/UP 27
-
Vcc
GND
28 24
7, 14
7, 12
PE12016G / PE12024G
Incremental Encoder
I/O Description
Input Reset input for the 24-bit counter
(PE12024G only)
Input
Input
Input
Input
Input
Input
Clock.
Used for internal synchronisation and
control timing.
Byte select.
A high level selects the least significant
byte. /A1=1 with PE12024G
A low level selects the most significant
byte (/A1=High with the PE12024G) –
see Table 2.
Byte select.
A low level with /A0=High selects the
MS-byte (Bits 16-23) on the PE12024G
Device Reset.
When active (low), the control logic is
reset to a known state and the counter is
cleared.
Write enable.
When /WE and /CS are active (low), the
data that is on the bus is loaded into the
counter.
Cascade Input for counting down.
(PE12016G only)
Input Cascade Input for counting up.
(PE12016G only)
Power Supply voltage
Ground
December 15, 2005 (Version 1.7)
Seite 12 / 25
PE12016G/24G

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