PDF D4701A Data sheet ( Hoja de datos )

Número de pieza	D4701A
Descripción	UPD4701A
Fabricantes	NEC
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No Preview Available ! DATA SHEET MOS INTEGRATED CIRCUIT µPD4701A INCREMENTAL ENCODER COUNTER DESCRIPTION The µPD4701A is a counter for an X, Y 2-axis incremental encoder. When a two-phase encoder signal is input for the X and Y axes, direction discrimination and computation is performed, and count data is output in 8-bit parallel form. In addition, a 3-contact-point input buffer is incorporated, which is useful for applications which use a pointing device such as a mouse or track-ball. The CPU checks the switch input flag or count flag and reads the 12-bit count data in two operations, one for the lower byte and one for the upper byte. The key input flag is output together with the count data in the upper byte. FEATURES • X, Y 2-axis incremental encoder counter • Counter input (Schmitt-triggered input) X axis: Y axis: XA, YA, XB YB 2-phase 2-phase signal signal  4-multiplication count method used • Counters: 12-bit binary up/down counters (2 sets, X & Y) Reset value: 000H • Count data output: 8-bit parallel latch output × 2 (including key input flag) • On-chip 3-contact-point key input buffer circuit • CMOS • Single +5 V power supply PIN CONFIGURATION (Top View) PIN NAMES XA, YA : A-phase inputs XB, YB : B-phase inputs RIGHT  LEFT  Key inputs MIDDLE  XA XB RESET X YA 1 2 3 4 24 VDD 23 D7 22 D6 21 D5 CS X/Y U/L D0 to 7 CF SF : Chip Select : X/Y Counter Select : Upper/Lower Byte Select : Data outputs : Count flag : Count flag RESET RESET X Y  Counter reset inputs YB RESET Y RIGHT LEFT MIDDLE SF 5 6 7 8 9 10 20 D4 19 D3 18 D2 17 D1 16 D0 15 CS CF 11 14 X/Y VSS 12 13 U/L wwwD(O.Do.caDutm.aSNehnoet. eNtICo4U.-6.I9nC4e-7t3A3)03 (1st edition) Date Published March 1997 P Printed in Japan © 1993 1 page µPD4701A 3. SWITCH INPUT OPERATION The µPD4701A can process up to 3 contact points as switch inputs (active-“L” input). Switch input is read as part of the count data upper byte together with the switch flag status as an internal status (see Fig. 3). These are all active- “H” outputs. The switch flag status, SF, is equivalent to the switch flag output, SF, described below. Fig. 3 Data Output Format Bit No. Upper Byte 7 65 43210 SF L R M C11 C10 C9 C8 Bit No. Lower Byte 7 65 43210 C7 C6 C5 C4 C3 C2 C1 C0 SF : Switch Flag L : Left Switch R : Right Switch M : Middle Switch C11 - 0 : Count Data (12 bit ) 4. OPERATION OF SWITCH FLAG, SF The switch flag, SF, becomes active (active-“L” output) when the RIGHT, LEFT or MIDDLE switch input is “L”. SF can also be read as the switch flag status together with the count data. 5. DATA READ OPERATION The CPU reads the count data and switch input status by controlling CS, X/Y and U/L. The relation between these is shown in Table 1. (At this time, the data latched on the falling edge of CS is output. If X/Y or U/L is switched while CS is still “L”, the data at the point at which CS changes from “H” to “L” is read. When CS is set to “H”, new data is read into the latch, and the new data is confirmed on the next fall of CS. Table 1 Data Output Table CS X/Y U/L D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 XC7 XC6 XC5 XC4 XC3 XC2 XC1 XC0 0 0 1 SF L R M XC11 XC10 XC9 XC8 0 1 0 YC7 YC6 YC5 YC4 YC3 YC2 YC1 YC0 0 1 1 SF L R M YC11 YC10 YC9 YC8 1×× FLOATING 5 5 Page Fig. 6 Two-Phase Signal & Switch Signal Input Timing tCYAB µPD4701A     XA, YA  XB, YB      RIGHT LEFT MIDDLE tPWABH tPWABL tSAB tSAB tSAB tSAB tPWSWL tPWSWH RESET X, Y tPWRS  XA, B YA, B     CF tDCTCL CS Fig. 7 Count Flag Output Timing tSCTEN tDABCF tSCSCF tSCT tSAB tDCSCF tHABCS tPWCS 11 11 Page

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