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PDF CY2XF33 Data sheet ( Hoja de datos )
| Número de pieza | CY2XF33 | |
| Descripción | High-Performance LVDS Oscillator | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY2XF33
High-Performance LVDS Oscillator With
Frequency Margining – Pin Control
Features
■ Low jitter crystal oscillator (XO)
■ Less than 1 ps typical RMS phase jitter
■ Differential LVDS output
■ Output frequency from 50 MHz to 690 MHz
■ Two frequency margining control pins (FS0, FS1)
■ Factory configured or field programmable
■ Integrated phase-locked loop (PLL)
■ Supply voltage: 3.3 V or 2.5 V
■ Pb-free package: 5.0 × 3.2 mm LCC
■ Commercial and industrial temperature ranges
Logic Block Diagram
Functional Description
The CY2XF33 is a high-performance and high-frequency crystal
oscillator (XO). It uses a Cypress proprietary low-noise PLL to
synthesize the frequency from an integrated crystal. The output
frequency can be changed through two select pins, allowing
easy frequency margin testing in applications.
The CY2XF33 is available as a factory configured device or as
a field programmable device.
FS1 1
FS0 2
Crystal
Oscillator
Low-Noise PLL
Output
Divider
Frequency Select
Decode
4 CLK
5 CLK#
Pinouts
Figure 1. Pin Diagram – 6-Pin Ceramic LCC
FS1 1
FS0 2
VSS 3
6 VDD
5 CLK#
4 CLK
Table 1. Pin Definitions – 6-Pin Ceramic LCC
Pin
1, 2
4, 5
6
3
Name
FS1, FS0
CLK, CLK#
VDD
VSS
I/O Type
CMOS input
LVDS output
Power
Power
Frequency select
Differential output clock
Supply voltage: 2.5 V or 3.3 V
Ground
Description
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4NUu.nmebt er: 001-53148 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 13, 2011
1 page  
CY2XF33
Absolute Maximum Conditions
Parameter
Description
Condition
VDD
VIN[1]
TS
TJ
ESDHBM
JA[2]
Supply voltage
–
Input voltage, DC
Temperature, storage
Relative to VSS
Non operating
Temperature, junction
–
ESD protection (human body model) JEDEC STD 22-A114-B
Thermal resistance, junction to ambient 0 m/s airflow
Min
–0.5
–0.5
–55
–40
2000
Max
4.4
VDD + 0.5
135
135
–
64
Unit
V
V
C
C
V
C/W
Operating Conditions
Parameter
Description
VDD 3.3 V supply voltage range
2.5 V supply voltage range
TPU Power up time for VDD to reach minimum specified voltage (power ramp is
monotonic)
TA Ambient temperature (commercial)
Ambient temperature (industrial)
Min Typ Max
3.135 3.3 3.465
2.375 2.5 2.625
0.05 –
500
0–
–40 –
70
85
Unit
V
V
ms
C
C
DC Electrical Characteristics
Parameter
Description
IDD[3]
Operating supply current
VOD
VOD
VOS
VOS
VIH
VIL
IIH0
IIH1
IIL0
IIL1
CIN0[4]
CIN1[4]
LVDS differential output voltage
Change in VOD between
complementary output states
LVDS offset output voltage
Change in VOS between
complementary output states
Input high voltage
Input low voltage
Input high current, FS0 pin
Input high current, FS1 pin
Input low current, FS0 pin
Input low current, FS1 pin
Input capacitance, FS0 pin
Input capacitance, FS1 pin
Condition
Min Typ Max
VDD = 3.465 V, CLK = 150 MHz, output
terminated
–
– 120
VDD = 2.625 V, CLK = 150 MHz, output
terminated
–
– 115
VDD = 3.3 V or 2.5 V, defined in Figure 3 247 – 454
as terminated in Figure 2
VDD = 3.3 V or 2.5 V, defined in Figure 3
as terminated in Figure 2
–
– 50
VDD = 3.3 V or 2.5 V, defined in Figure 4 1.125 – 1.375
as terminated in Figure 2
VDD = 3.3 V or 2.5 V, RTERM = 100 – – 50
between CLK and CLK#
–
–
Input = VDD
Input = VDD
Input = VSS
Input = VSS
–
0.7 ×
–
–
VDD
– – 0.3 ×
VDD
– – 115
– – 10
–50 –
–
–20 –
–
– 15 –
– –4–
Unit
mA
mA
mV
mV
V
mV
V
V
A
A
A
A
pF
pF
Notes
1. The voltage on any input or I/O pin cannot exceed the power pin during power up.
2. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers
are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
3. IDD includes ~4 mA of current that is dissipated externally in the output termination resistors.
4. Not 100% tested, guaranteed by design and characterization.
Document Number: 001-53148 Rev. *E
Page 5 of 12
5 Page 
CY2XF33
Document History Page
Document Title: CY2XF33 High-Performance LVDS Oscillator With Frequency Margining – Pin Control
Document Number: 001-53148
Revision
ECN
Orig. of Submission
Change
Date
Description of Change
** 2704379 KVM/PYRS 05/11/2009 New data sheet
*A 2734005 WWZ 07/09/2009 Post to external web
*B
2764787
KVM 09/18/2009 Change VOD limits from 250/450 mV to 247/454 mV
Add max limit for TR, TF: 1.0 ns
Change TLOCK max from 10 ms to 5 ms
Change TLFS max from 10 ms to 1 ms
*C
2898472
KVM 03/24/2010 Moved ‘xxx’ parts to Possible Configurations table.
Updated package diagram.
*D 3165931 BASH 02/10/2011 Removed “Preliminary” tag from the document.
Added “Application Specific Factory Configurations” section.
Added application specific part numbers and note in Ordering Code
Information.
*E 3279652 BASH 06/13/2011 Swapped FS0 and FS1 in Logic Block Diagram, Pinouts and Pin Definition on
page 1.
Removed CY2XF33LXC533T from “Application Specific Factory
Configurations” and “Ordering Information table.”
Document Number: 001-53148 Rev. *E
Page 11 of 12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CY2XF33.PDF ] | |
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