|
|
PDF CY2XF32 Data sheet ( Hoja de datos )
| Número de pieza | CY2XF32 | |
| Descripción | High Performance CMOS Oscillator | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY2XF32 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
|
No Preview Available !
CY2XF32
High Performance CMOS Oscillator with
Frequency Margining – Pin Control
Features
■ Crystal oscillator with CMOS output
■ Output frequency from 8 MHz to 200 MHz
■ Two frequency margining control pins (FS0, FS1)
■ Output enable or power-down function
■ Factory configured or field programmable
■ Integrated phase-locked loop (PLL)
■ Supply voltage: 3.3 V or 2.5 V
■ Pb-free package: 5.0 × 3.2 mm LCC
■ Commercial and industrial temperature ranges
Logic Block Diagram
CRYSTAL
OSCILLATOR
FS1 2
FS0 5
OE/PD# 1
Functional Description
The CY2XF32 is a high performance and high frequency crystal
oscillator (XO). It uses a Cypress proprietary low noise PLL to
synthesize the frequency from an integrated crystal. The output
frequency can be changed via two select pins, allowing easy
frequency margin testing in applications.
The CY2XF32 is available as a factory configured device or as
a field programmable device.
LOW -NOISE
PLL
OUTPU T
DI VI DE R
FR EQU EN C Y
SELECT DECODE
4 CLK
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4NUu.nmebt er: 001-53147 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 6, 2011
[+] Feedback
1 page  
CY2XF32
AC Electrical Characteristics[3]
Parameter
FOUT
FSC
FSI
AG
TDC
TR
TF
TOHZ
TOE
TLOCK
TLFS
Description
Output Frequency[5]
Frequency Stability, Commercial
Devices[4]
Frequency Stability, Industrial
Devices[4]
Aging, 10 Years
Output Duty Cycle
Output Rise Time
Output Fall Time
Output Disable Time
Output Enable Time
Startup Time
Relock Time
Condition
TA = 0°C to 70°C
TA = –40°C to 85°C
Measured at VDD/2; see Figure 2
20% to 80% of VDD, CLOAD = 15 pF
80% to 20% of VDD, CLOAD = 15 pF
Time from falling edge on OE to stopped
outputs (Asynchronous)
Time from rising edge on OE to outputs at
a valid frequency (Asynchronous)
Time for CLK to reach valid frequency
measured from the time
VDD = VDD(min.) or from PD# rising edge
Time for CLK to reach valid frequency from
FS0 or FS1 pin change
Min
8
–
–
–
45
–
–
–
–
–
–
Typ Max
– 200
– ±35
– ±55
– ±15
50 55
0.7 1.5
0.8 1.5
– 100
– 100
–5
–1
Unit
MHz
ppm
ppm
ppm
%
ns
ns
ns
ns
ms
ms
Notes
4. Frequency stability is the maximum variation in frequency from F0. It includes initial accuracy, plus variation from temperature and supply voltage.
5. This parameter is specified in CyberClocks Online software.
Document Number: 001-53147 Rev. *D
Page 5 of 10
[+] Feedback
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CY2XF32.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY2XF32 | High Performance CMOS Oscillator | Cypress Semiconductor |
| CY2XF33 | High-Performance LVDS Oscillator | Cypress Semiconductor |
| CY2XF34 | High Performance LVPECL Oscillator | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |