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ADP5042 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP5042
Beschreibung Micro PMU
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADP5042 Datasheet, Funktion
www.DataSheet4U.net
Micro PMU with 0.8 A Buck, Two 300 mA LDOs
Supervisory, Watchdog and Manual Reset
ADP5042
FEATURES
Input voltage range: 2.3 V to 5.5 V
One 0.8 A buck regulator
Two 300 mA LDOs
20-lead, 4 mm × 4 mm LFCSP package
Initial regulator accuracy: ±1%
Overcurrent and thermal protection
Soft start
Undervoltage lockout
Open drain processor reset with threshold monitoring
±1.5% threshold accuracy over the full temperate range
Guaranteed reset output valid to VCC = 1 V
Dual watchdog for secure systems
Watchdog 1 controls reset
Watchdog 2 controls reset and regulators power cycle
Buck key specifications
Current mode topology for excellent transient response
3 MHz operating frequency
Uses tiny multilayer inductors and capacitors
Mode pin selects forced PWM or auto PFM/PSM modes
100% duty cycle low dropout mode
LDOs key specifications
Low VIN from 1.7 V to 5.5 V
Stable with1 μF ceramic output capacitors
High PSRR, 60 dB PSRR up to 1 kHz/10 kHz
Low output noise
110 μV rms typical output noise at VOUT = 2.8 V
Low dropout voltage: 150 mV at 300 mA load
−40°C to +125°C junction temperature range
GENERAL DESCRIPTION
The ADP5042 combines one high performance buck regulator
and two low dropout regulators (LDO) in a small 20-lead
LFCSP to meet demanding performance and board space
requirements.
The high switching frequency of the buck regulator enables
use of tiny multilayer external components and minimizes the
board space.
The MODE pin selects the buck mode of operation. When set
to logic high, the buck regulators operate in forced PWM mode.
When the MODE pin is set to logic low, the buck regulators
operate in PWM mode when the load is around the nominal
value. When the load current falls below a predefined threshold
the regulator operates in power save mode (PSM) improving
the light-load efficiency.
HIGH LEVEL BLOCK DIAGRAM
RFILT = 30
VIN1 = 2.3V
TO 5.5V
C5
4.7µF
AVIN
VIN1
ON
OFF
EN1
VIN2 = 1.7V
TO 5.5V
C1
1µF
VIN2
ON
OFF
EN2
AVIN
BUCK
EN_BK
LDO1
(DIGITAL)
EN_LDO1
AVIN
VIN3 = 1.7V
TO 5.5V
C3
1µF
ON
OFF
MR
EN3
VIN3
EN_LDO2
LDO2
(ANALOG)
AGND
SW
VOUT1
PGND
L1
1µH
VOUT1 AT
C6 800mA
10µF
MODE
VOUT2
WSTAT
nRSTO
FPWM
PSM/PWM
VOUT2 AT
300mA
C2
1µF
WDI1
WDI2
VOUT3
VOUT3 AT
300mA
C4
1µF
Figure 1.
The low quiescent current, low dropout voltage, and wide input
voltage range of the ADP5042 LDOs extend the battery life of
portable devices. The two LDOs maintain power supply
rejection greater than 60 dB for frequencies as high as 10 kHz
while operating with a low headroom voltage.
Each regulator is activated by a high level on the respective
enable pin. The ADP5042 is available with factory programmable
default output voltages and can be set to a wide range of options.
The ADP5042 contains supervisory circuits that monitor
power supply voltage levels and code execution integrity in
microprocessor-based systems. They also provide power-on
reset signals. An on-chip dual watchdog timer can reset the
microprocessor or power cycle the system (Watchdog 2) if it
fails to strobe within a preset timeout period.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.






ADP5042 Datasheet, Funktion
ADP5042
Parameter
Load Regulation1
DROPOUT VOLTAGE2
ACTIVE PULL-DOWN
START-UP TIME
CURRENT-LIMIT THRESHOLD3
OUTPUT NOISE
POWER SUPPLY REJECTION RATIO
Symbol
∆VOUT2/∆IOUT2
∆VOUT3/∆IOUT3
VDROPOUT
RPDLDO
TSTART-UP
ILIMIT
OUTLDO2NOISE
OUTLDO1NOISE
PSRR
Conditions
IOUT2, VOUT3 = 1 mA to 200 mA
Min
IOUT2, VOUT3 = 1 mA to 200 mA
TJ = −40°C to +125°C
VOUT2, VOUT3 = 3.3 V
IOUT2, IOUT3 = 10 mA
IOUT2, IOUT3 = 10 mA, TJ = −40°C to +125°C
IOUT2, IOUT3 = 200 mA
IOUT2, IOUT3 = 200 mA, TJ = −40°C to +125°C
EN2/EN3 = 0 V
VOUT2, VOUT3 = 3.3 V
TJ = −40°C to +125°C
10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 3.3 V
10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 2.8 V
10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 1.5 V
10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 3.3 V
10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 2.8 V
10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 1.5 V
1 kHz, VIN2, VIN3 = 3.3 V, VOUT2, OUT3 = 2.8 V,
IOUT = 100 mA
100 kHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V,
IOUT = 100 mA
1 MHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V,
IOUT = 100 mA
335
Typ Max
0.002
Unit
%/mA
0.0075 %/mA
4
5
60
100
600
85
470
123
110
59
140
129
66
66
57
60
mV
mV
mV
mV
Ω
μs
mA
μV rms
μV rms
μV rms
μV rms
μV rms
μV rms
dB
dB
dB
1 Based on an end-point calculation using 1 mA and 100 mA loads.
2 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.3 V.
3 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 5.
Parameter
MINIMUM OUTPUT CAPACITANCE (BUCK)1
MINIMUM INPUT AND OUTPUT CAPACITANCE2 (LDO1, LDO2)
CAPACITOR ESR
Symbol
CMIN1
CMIN23
RESR
Conditions
TJ = −40°C to +125°C
TJ = −40°C to +125°C
TJ = −40°C to +125°C
Min Typ Max Unit
7 40 μF
0.70 μF
0.001
1 The minimum output capacitance should be greater than 4.7 μF over the full range of operating conditions. The full range of operating conditions in the application
must be considered during device selection to ensure that the minimum capacitance specification is met.
2 The minimum input and output capacitance should be greater than 0.70 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended,
Y5V and Z5U capacitors are not recommended for use with LDOs or the buck.
Rev. 0 | Page 6 of 32

6 Page









ADP5042 pdf, datenblatt
ADP5042
VOUT
2
ISW
3
SW
1
CH1 2.0V/DIV 1MBW 20.0M
CH2 50.0mV/DIV
BW 20.0M
CH3 500mA/DIV
BW 20.0M
A CH1
1.56mV
5.0µs/DIV
200MS/s
5.0ns/pt
Figure 21. Typical Waveforms, VOUT1 = 1.8 V, IOUT2 = 30 mA, Auto Mode
VOUT
2
ISW
3
SW
1
CH1 2.0V/DIV 1MBW 20.0M
CH2 50.0mV/DIV
BW 20.0M
CH3 500mA/DIV
BW 20.0M
A CH1
1.56mV
500ns/DIV
200MS/s
5.0ns/pt
Figure 22. Typical Waveforms, VOUT1 = 1.8 V, IOUT1 = 30 mA, PWM Mode
VOUT
1
ISW
2
SW
3
CH1 20.0mV/DIV
BW 20.0M A CH1
CH2 200mA/DIV 1MBW 20.0M
CH3 2.0V/DIV 1MBW 20.0M
2.4mV
200ns/DIV
500MS/s
2.0ns/pt
Figure 23. Typical Waveforms, VOUT1 = 3.3 V, IOUT2 = 30 mA, PWM Mode
VIN
VOUT
2
SW
1
3
CH1 3V/DIV
BW 20.0M
CH2 50mV/DIV
BW 20.0M
CH3 900mV/DIV 1MBW 20.0M
A CH3
4.79V
100µs/DIV
10.0MS/s
100ns/pt
Figure 24. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V,
VOUT1 = 3.3 V, PWM Mode
VIN
VOUT
2
SW
3
4
CH2 50mV/DIV
BW 20.0M A CH3
CH3 1V/DIV 1MBW 20.0M
CH4 2V/DIV 1MBW 20.0M
4.96mV 100µs/DIV
20MS/s
100ns/pt
Figure 25. Buck Response to Line Transient, VIN = 4.5 V to 5.0 V, VOUT1 = 1.8 V,
PWM Mode
SW
1
VOUT
2
IOUT
3
CH1 4V/DIV
BW 20.0M
CH2 50mV/DIV 1MBW 20.0M
CH3 50mA/DIV 1MBW 20.0M
A CH3 44mA 200µs/DIV
10MS/s
100ns/pt
Figure 26. Buck Response to Load Transient, IOUT1 from 1 mA to 50 mA,
VOUT1 = 3.3 V, Auto Mode
Rev. 0 | Page 12 of 32

12 Page





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