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PDF ADN4605 Data sheet ( Hoja de datos )
| Número de pieza | ADN4605 | |
| Descripción | 4.25 Gbps 40 X 40 Digital Crosspoint Switch | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
DC to 4.25 Gbps per port NRZ data rate
Adjustable receive equalization
3 dB, 6 dB, or 12 dB boost
Compensates over 40 inches of FR4 at 4.25 Gbps
Adjustable transmit preemphasis/deemphasis
Programmable boost and output level
Compensates over 40 inches of FR4 at 4.25 Gbps
Low power
105 mW per channel at 2.5 V (400 mV p-p differential
output level swing)
40 × 40, fully differential, nonblocking array
Double rank connection programming with dual maps
Low jitter, typically <25 ps
Flexible 2.5 V to 3.3 V supply range
DC- or ac-coupled differential PECL/CML inputs
Differential CML outputs
Per-lane polarity inversion for routing ease
50 Ω on-chip I/O termination with disable feature
Supports 8b10b, scrambled or uncoded NRZ data
Serial (IC slave or SPI) control interface
Parallel control interface
APPLICATIONS
Digital video (HDMI, DVI, DisplayPort, 3G/HD/SD-SDI)
Fiber optic network switching
High speed serial backplane routing to OC-48 with FEC
XAUI, 4x Fibre Channel, Infiniband®, and GbE over backplane
Data storage networks
GENERAL DESCRIPTION
The ADN4605 is a 40 × 40 asynchronous, protocol agnostic,
digital crosspoint switch, with 40 differential PECL/CML-
compatible inputs and 40 differential programmable CML
outputs.
The ADN4605 is optimized for NRZ signaling with data rates of
up to 4.25 Gbps per port. Each port offers adjustable levels of
input equalization, programmable output swing, and output
preemphasis/deemphasis.
4.25 Gbps 40 × 40 Digital
Crosspoint Switch
ADN4605
FUNCTIONAL BLOCK DIAGRAM
DVCC
VCC
IP[39:0]
VTTIA,
VTTIB
IN[39:0]
Rx Tx
EQ
40 × 40
SWITCH
MATRIX
PRE-
EMPHASIS
OP[39:0]
VTTOA,
VTTOB
ON[39:0]
EQUALIZATION
SETTINGS
CONNECTION
MAP 1
CONNECTION
MAP 0
OUTPUT
LEVEL
SETTINGS
PRE-
EMPHASIS
LEVEL
SETTINGS
RESET
SER/PAR
I2C/SPI
(UPDATE)
CS
SCL/SCK/
WE
SDI/RE
PARALLEL/SERIA L CONTROL
LOGIC INTERFACE
VEE
Figure 1.
ADN4605
DATA[0]/
SDA/SDO
DATA[1]
(UPDATE)
DATA[7:2]
ADDR[7:0]
The ADN4605 nonblocking switch core implements a 40 × 40
crossbar and supports independent channel switching through
serial and parallel control interfaces. The ADN4605 has low
latency and very low channel-to-channel skew.
An I2C, SPI, or parallel interface is used to communicate with
the device for control of connectivity and other features.
The ADN4605 is assembled in a 35 mm × 35 mm, 352 BGA
package and operates over a temperature range of −40°C
to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
1 page  
ADN4605
I2C TIMING SPECIFICATIONS
SDA
tf
tLOW
tr tSU;DAT
tf
tHD;STA
tSP tr
tBUF
SCL
tHD;STA
S
tHD;DAT
tHIGH
tSU;STA
Sr
Figure 2. I2C Timing Diagram
Table 2. I2C Timing Specifications
Parameter
SCL Clock Frequency
Hold Time for a Start Condition
Setup Time for a Repeated Start Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Data Hold Time
Data Setup Time
Rise Time for Both SDA and SCL
Fall Time for Both SDA and SCL
Setup Time for Stop Condition
Bus Free Time Between a Stop Condition and a Start Condition
Bus Idle Time After a Reset
Reset Pulse Width
Symbol
fSCL
tHD; STA
tSU; STA
tLOW
tHIGH
tHD; DAT
tSU; DAT
tr
tf
tSU; STO
tBUF
tSU;STO
Min
0
0.5
0.5
0.6
0.02
0.02
1
1
0.5
1
20
20
SPI TIMING SPECIFICATIONS
CS
t1
t2
SCLK
DIN
t3 t5 t6
D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X
DOUT
t4
X X X X X X X X D7 D6 D5 D4 D3 D2 D1
Figure 3. SPI Timing Diagram
Table 3. SPI Timing Specifications
Parameter
SCK Clock Frequency
CS to SCLK Setup Time
SCLK High Pulse Width
SCLK Low Pulse Width
Data Access Time After SCLK Falling Edge
Data Setup Time Prior to SCLK Rising Edge
Data Hold Time After SCLK Rising Edge
CS to SCLK Hold Time
CS to SDO High Impedance
Reset Pulse Width
Symbol
fSCK
t1
t2
t3
t4
t5
t6
t7
t8
Min
0
30
30
10
30
0
20
PS
Max
500+
1.4
300
300
Unit
kHz
μs
μs
μs
μs
μs
μs
ns
ns
μs
ns
ns
ns
t7
X
t8
D0
Max Unit
10 MHz
ns
ns
ns
45 ns
ns
ns
ns
45 ns
ns
Rev. 0 | Page 5 of 56
5 Page 
Pin No.
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
E1
E2
E3
E4
E23
E24
E25
E26
F1
F2
F3
F4
F23
F24
F25
F26
G1
G2
G3
G4
G23
G24
G25
G26
H1
H2
H3
H4
H23
H24
Mnemonic
VEE
VEE
VEE
VCC
VCC
VEE
VEE
VEE
VEE
VCC
DVCC
VCC
VEE
IN39
IN1
IP2
VCC
VEE
VEE
VCC
IN38
IP39
IP3
IN2
VTTIA
VEE
VEE
VTTIB
IP38
IN37
IN3
IP4
VTTIA
VEE
VEE
VTTIB
IN36
IP37
IP5
IN4
VTTIA
VEE
WE/SCL/SCK
VTTIB
ADN4605
Type
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Input
Input
Input
Power
Power
Power
Power
Input
Input
Input
Input
Power
Power
Power
Power
Input
Input
Input
Input
Power
Power
Power
Power
Input
Input
Input
Input
Power
Power
Control
Power
Description
Negative Supply.
Negative Supply.
Negative Supply.
Positive Supply.
Positive Supply.
Negative Supply.
Negative Supply.
Negative Supply.
Negative Supply.
Positive Supply.
Digital Positive Supply.
Positive Supply.
Negative Supply.
High Speed Input Complement.
High Speed Input Complement.
High Speed Input.
Positive Supply.
Negative Supply.
Negative Supply.
Positive Supply.
High Speed Input Complement.
High Speed Input
High Speed Input
High Speed Input Complement.
Input Termination Supply (A). The VTTIA pins are normally tied to the
VTTIB pins.
Negative Supply.
Negative Supply.
Input Termination Supply (B). The VTTIB pins are normally tied to the
VTTIA pins.
High Speed Input.
High Speed Input Complement.
High Speed Input Complement.
High Speed Input.
Input Termination Supply (A). The VTTIA pins are normally tied to the
VTTIB pins.
Negative Supply.
Negative Supply.
Input Termination Supply (B). The VTTIB pins are normally tied to the
VTTIA pins.
High Speed Input Complement.
High Speed Input.
High Speed Input.
High Speed Input Complement.
Input Termination Supply (A). The VTTIA pins are normally tied to the
VTTIB pins.
Negative Supply.
Parallel control interface: First-Rank Write Strobe (WE) Active Low.
I2C Control Interface: I2C Clock (SCL).
SPI Control Interface: SPI Clock (SCK).
Input Termination Supply (B). The VTTIB pins are normally tied to the
VTTIA pins.
Rev. 0 | Page 11 of 56
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADN4605.PDF ] | |
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