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PDF ADM1168 Data sheet ( Hoja de datos )
| Número de pieza | ADM1168 | |
| Descripción | Super Sequencer and Monitor | |
| Fabricantes | Analog Devices | |
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Data Sheet
Super Sequencer and Monitor with
Nonvolatile Fault Recording
ADM1168
FEATURES
Complete supervisory and sequencing solution for up to
8 supplies
16 event deep black box nonvolatile fault recording
8 supply fault detectors enable supervision of supplies to
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures
4 selectable input attenuators allow supervision of supplies to
14.4 V on VH
6 V on VP1 to VP3 (VPx)
4 dual-function inputs, VX1 to VX4 (VXx)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
8 programmable driver outputs, PDO1 to PDO8 (PDOx)
Open-collector with external pull-up
Push/pull output, driven to VDDCAP or VPx
Open-collector with weak pull-up to VDDCAP or VPx
Internally charge-pumped high drive for use with external
NFET (PDO1 to PDO6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Device powered by the highest of VPx, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 32-lead, 7 mm × 7 mm LQFP
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
REFOUT REFGND SDA SCL A1 A0
ADM1168
VREF
SMBus
INTERFACE
FAULT RECORDING EEPROM
VX1
VX2
VX3
VX4
VP1
VP2
VP3
VH
AGND
VDDCAP
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
SEQUENCING
ENGINE
CONFIGURABLE
OUTPUT
DRIVERS
(HV CAPABLE OF
DRIVING GATES
OF NFET)
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
VDD
ARBITRATOR
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDOGND
VCCP GND
Figure 1.
GENERAL DESCRIPTION
The ADM1168 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple supply systems.
The device also provides up to eight programmable inputs
for monitoring undervoltage faults, overvoltage faults, or
out-of-window faults on up to eight supplies. In addition, eight
programmable outputs can be used as logic enables. Six of these
programmable outputs can also provide up to a 12 V output for
driving the gate of an NFET that can be placed in the path of a
supply.
The logical core of the device is a sequencing engine. This state
machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs based
on the condition of the inputs.
A block of nonvolatile EEPROM is available that can be used to
store user-defined information and may also be used to hold a
number of fault records that are written by the sequencing engine
defined by the user when a particular fault or sequence occurs.
The ADM1168 is controlled via configuration data that can be
programmed into an EEPROM. The whole configuration can be
programmed using an intuitive GUI-based software package
provided by Analog Devices, Inc.
For more information about the ADM1168 register map, refer
to the AN-721 Application Note.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADM1168
Data Sheet
SPECIFICATIONS
VH = 3.0 V to 14.4 V1, VPx = 3.0 V to 6.0 V1, TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
POWER SUPPLY ARBITRATION
VH, VPx
VPx
VH
VDDCAP
CVDDCAP
POWER SUPPLY
Supply Current, IVH, IVPx
Additional Currents
All PDOx FET Drivers On
Current Available from VDDCAP
EEPROM Erase Current
SUPPLY FAULT DETECTORS
VH Pin
Input Impedance
Input Attenuator Error
Detection Ranges
High Range
Midrange
VPx Pins
Input Impedance
Input Attenuator Error
Detection Ranges
Midrange
Low Range
Ultralow Range
VXx Pins
Input Impedance
Detection Ranges
Ultralow Range
Absolute Accuracy
Threshold Resolution
Digital Glitch Filter
REFERENCE OUTPUT
Reference Output Voltage
Load Regulation
Minimum Load Capacitance
PSRR
Min Typ Max Unit Test Conditions/Comments
3.0 V Minimum supply required on one of the VH, VPx pins
6.0 V Maximum VDDCAP = 5.1 V typical
14.4 V VDDCAP = 4.75 V
2.7 4.75 5.4 V Regulated LDO output
10 μF Minimum recommended decoupling capacitance
4.2 6
mA VDDCAP = 4.75 V, PDO1 to PDO8 off
1
2
10
mA VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 μA each,
PDO7 to PDO8 off
mA Maximum additional load that can be drawn from all PDO
pull-ups to VDDCAP
mA 1 ms duration only, VDDCAP = 3 V
6
2.5
2.5
1.25
0.573
1
0.573
2.043
1
52
±0.05
kΩ
% Midrange and high range
14.4 V
6V
52
±0.05
kΩ
% Low range and midrange
6
3
1.375
V
V
V
No input attenuation error
MΩ
1.375 V No input attenuation error
±1 % Internal reference VREF error + DAC nonlinearity +
comparator offset error
8 Bits
0 μs Minimum programmable filter length
100 μs Maximum programmable filter length
2.048
−0.25
0.25
60
2.053
V
mV
mV
μF
dB
No load
Sourcing current
Sinking current
Capacitor required for decoupling, stability
DC
Rev. B | Page 4 of 27
5 Page 
ADM1168
POWERING THE ADM1168
The ADM1168 is powered from the highest voltage input on either
the positive-only supply inputs (VPx) or the high voltage supply
input (VH). This technique offers improved redundancy because
the device is not dependent on any particular voltage rail to keep
it operational. The same pins are used for supply fault detection
(see the Supply Supervision section). A VDD arbitrator on the
device chooses which supply to use. The arbitrator can be
considered an OR’ing of four low dropout regulators (LDOs)
together. A supply comparator chooses the highest input to
provide the on-chip supply. There is minimal switching loss
with this architecture (~0.2 V), resulting in the ability to power
the ADM1168 from a supply as low as 3.0 V. Note that the supply
on the VXx pins cannot be used to power the device.
An external capacitor to GND is required to decouple the on-chip
supply from noise. This capacitor should be connected to the
VDDCAP pin, as shown in Figure 14. The capacitor has another
use during brownouts (momentary loss of power). Under these
conditions, when the input supply (VPx or VH) dips transiently
below VDD, the synchronous rectifier switch immediately turns off
so that it does not pull VDD down. The VDD capacitor can then
act as a reservoir to keep the device active until the next highest
supply takes over the powering of the device. A 10 μF capacitor is
recommended for this reservoir/decoupling function.
The value of the VDDCAP capacitor may be increased if it is
necessary to guarantee a complete fault record is written into
EEPROM should all supplies fail. The value of the capacitor to
use is discussed in the Black Box Writes with No External
Supply section.
The VH input pin can accommodate supplies up to 14.4 V, which
allows the ADM1168 to be powered using a 12 V backplane supply.
In cases where this 12 V supply is hot swapped, it is recommended
that the ADM1168 not be connected directly to the supply. Suitable
precautions, such as the use of a hot swap controller or RC filter
network, should be taken to protect the device from transients
that may cause damage during hot swap events.
Data Sheet
When two or more supplies are within 100 mV of each other,
the supply that first takes control of VDD keeps control. For
example, if VP1 is connected to a 3.3 V supply, VDD powers up
to approximately 3.1 V through VP1. If VP2 is then connected
to another 3.3 V supply, VP1 still powers the device, unless VP2
goes 100 mV higher than VP1.
VDDCAP
VP1 IN OUT
4.75V
LDO
EN
VP2 IN OUT
4.75V
LDO
EN
VP3 IN OUT
4.75V
LDO
EN
INTERNAL
VH
IN OUT
DEVICE
4.75V
SUPPLY
LDO
EN
SUPPLY
COMPARATOR
Figure 14. VDD Arbitrator Operation
SLEW RATE CONSIDERATION
When the ambient temperature of operation is less than
approximately −20°C, and in the event of a power loss where all
supply inputs fail for less than a few hundreds of milliseconds
(for example, due to a system supply brownout), it is recommended
that the supply voltage recover with a ramp rate of at least
1.5 V/ms or less than 0.5 V/ms.
Rev. B | Page 10 of 27
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet ADM1168.PDF ] | |
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