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PDF ADATE209 Data sheet ( Hoja de datos )
| Número de pieza | ADATE209 | |
| Descripción | 4.0 Gbps Dual Driver | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
>4.0 Gbps (2 V swings)
120 ps rise time/fall time (2 V swings)
<1.0 W for dual driver (<500 mW/channel)
−1 V to +3.5 V range
Fast termination mode (VTx)
Cable loss compensation
APPLICATIONS
Automatic test equipment
Semiconductor test systems
Board test systems
Instrumentation and characterization equipment
High speed memory testing (DDR2/DDR3/DDR4)
HDMI testing
GENERAL DESCRIPTION
The ADATE209 is a dual pin driver designed for testing DDR2,
DDR3, and DDR4. It can also be used for high speed SoC applica-
tions, such as testing PCI Express 1.0 and HDMI™. The device is a
three-level driver capable of high fidelity swings from 200 mV
to 4 V over a −1 V to +3.5 V range. It has rise/fall times (20% to
80%) under 120 ps for a 2 V programmed swing and 150 ps for
4.0 Gbps Dual Driver
ADATE209
FUNCTIONAL BLOCK DIAGRAM
VH1
VL1
VT1
DA1
DB1
TERM1
DROUT1
DA2
DB2
TERM2
CLC1EN
VH2
VL2
VT2
DROUT2
CLC2EN
Figure 1.
a 3 V programmed swing, and is capable of supporting data
rates of 4.4 Gbps and 3.2 Gbps, respectively.
The device is capable of high speed transitions into and out of
termination mode. It also contains peaking/pre-emphasis circuitry.
The ADATE209 is available in an 8 mm × 8 mm, 49-ball
CSP_BGA.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
1 page  
ADATE209
Parameter
Dynamic Performance, Drive (VHx to VLx)
Propagation Delay Time
Propagation Delay Temperature
Coefficient
Delay Matching, Edge to Edge
Delay Change vs. Duty Cycle
Min
300
Preshoot and Undershoot
Settling Time (VHx to VLx)
To Within 3% of Final Value
To Within 1% of Final Value
Rise/Fall Times (VTx to/from VHx/VLx)
1.0 V Programmed Swing
2.0 V Programmed Swing
Dynamic Performance, VTERM
(VHx or VLx to/from VTx)
Propagation Delay Time
Cable Loss Compensation
Logic Control Inputs, CLCxEN
Logic High
Logic Low
ICLCxEN
Compensation Constants
Boost Time Constant
0
0.9
0
−10
Boost Peaking Amplifier
1 See the Explanation of Test Levels section.
Typ Max Unit
660 1400 ps
0.7 ps/ºC
Test
Level1
II/V
III
Test Conditions/Comments
Toggle DAx inputs
VHx = 2.0 V, VLx = 0.0 V, terminated
VHx = 2.0 V, VLx = 0.0 V, terminated
±15
ps V
VHx = 2.0 V, VLx = 0.0 V, terminated, rising vs. falling
±10
ps V
VHx = 2.0 V, VLx = 0.0 V, terminated, 5% to 95%
duty cycle
10
mV V
VHx = 2.0 V, VLx = 0.0 V, terminated
Toggle DAx Inputs
0.4
ns V
VHx = 2.0 V, VLx = 0.0 V, terminated
2
ns V
VHx = 2.0 V, VLx = 0.0 V, terminated
Toggle DAx inputs
110
ps V
VHx = 1.0 V, VTx = 0.5V, VLx = 0.0 V, terminated,
20% to 80%
170
ps V
VHx = 2.0 V, VTx = 1.0 V, VLx = 0.0 V, terminated,
20% to 80%
Toggle TERMx inputs
720
ns V
VHx = 3.0 V, VTx = 1.5 V, VLx = 0.0 V, terminated
3.3
3.3
0.7
±1.2 +10
V
V
V
μA
I
IV
IV
II
VIN = 0.0 V and 3.3 V
275
ps V
CLCxEN = 3.3 V, VHx = 1.0 V, VLx = 0.0 V,
terminated
18 % V CLCxEN = 3.3 V, VHx = 1.0 V, VLx = 0.0 V,
terminated
Rev. 0 | Page 5 of 16
5 Page 
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
TIME (ns)
Figure 15. VHx = 2.0 V, VTx = 1.0 V, VLx = 0.0 V,
Transitions Between VHx/VLx and VTx
30
20
10
NEGATIVE PULSE
0
–10 POSITIVE PULSE
–20
–30
0.1 1 10
PULSE WIDTH (ns)
Figure 16. 1 V Minimum Pulse Width (VHx = 1.0 V, VLx = 0.0 V), CLC Disabled
30
20
NEGATIVE PULSE
10
POSITIVE PULSE
0
–10
–20
–30
0.1
1
PULSE WIDTH (ns)
10
Figure 17. 2 V Minimum Pulse Width (VHx = 2.0 V, VLx = 0.0 V), CLC Disabled
ADATE209
30
20
NEGATIVE PULSE
10
0
POSITIVE PULSE
–10
–20
–30
0.1
1
PULSE WIDTH (ns)
10
Figure 18. 3 V Minimum Pulse Width (VHx = 3.0 V, VLx = 0.0 V), CLC Disabled
5
0
–5
–10
50°C
–15
70°C
–20 90°C
–25
–2 –1
0
1
2
3
4
VHx (V)
Figure 19. Driver Linearity (VHx), VLx = −1.1 V, VTx = 1.0 V
4
3
90°C
2 70°C
50°C
1
0
–1
–2
–3
–2 –1
0
1
2
3
4
VLx (V)
Figure 20. Driver Linearity (VLx), VHx = 3.6 V, VTx = 1.0 V
Rev. 0 | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADATE209.PDF ] | |
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