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PDF AD9837 Data sheet ( Hoja de datos )
| Número de pieza | AD9837 | |
| Descripción | Programmable Waveform Generator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9837 (archivo pdf) en la parte inferior de esta página. Total 29 Páginas | ||
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Data Sheet
FEATURES
Digitally programmable frequency and phase
8.5 mW power consumption at 2.3 V
MCLK speed: 16 MHz (B grade), 5 MHz (A grade)
28-bit resolution: 0.06 Hz at 16 MHz reference clock
Sinusoidal, triangular, and square wave outputs
2.3 V to 5.5 V power supply
3-wire SPI interface
Extended temperature range: −40°C to +125°C
Power-down option
10-lead LFCSP
APPLICATIONS
Frequency stimulus/waveform generation
Liquid and gas flow measurement
Sensory applications: proximity, motion,
and defect detection
Line loss/attenuation
Test and medical equipment
Sweep/clock generators
Time domain reflectometry (TDR) applications
Low Power, 8.5 mW, 2.3 V to 5.5 V,
Programmable Waveform Generator
AD9837
GENERAL DESCRIPTION
The AD9837 is a low power, programmable waveform generator
capable of producing sine, triangular, and square wave outputs.
Waveform generation is required in various types of sensing,
actuation, and time domain reflectometry (TDR) applications.
The output frequency and phase are software programmable,
allowing easy tuning. The frequency registers are 28 bits wide:
with a 16 MHz clock rate, resolution of 0.06 Hz can be achieved;
with a 5 MHz clock rate, the AD9837 can be tuned to 0.02 Hz
resolution.
The AD9837 is written to via a 3-wire serial interface. This serial
interface operates at clock rates up to 40 MHz and is compatible
with DSP and microcontroller standards. The device operates
with a power supply from 2.3 V to 5.5 V.
The AD9837 has a power-down (sleep) function. Sections of the
device that are not being used can be powered down to minimize
the current consumption of the part. For example, the DAC can
be powered down when a clock output is being generated.
The AD9837 is available in a 10-lead LFCSP_WD package.
AGND DGND
FUNCTIONAL BLOCK DIAGRAM
VDD
CAP/2.5V
MCLK
AVDD/
DVDD
REGULATOR
2.5V
ON-BOARD
REFERENCE
FULL-SCALE
CONTROL
28-BIT FREQ0 REG
28-BIT FREQ1 REG
MUX
PHASE
ACCUMUL ATOR
(28-BIT)
12-BIT PHASE0 REG
12-BIT PHASE1 REG
MUX
16-BIT CONTROL REGISTER
SERIAL INTERFACE
AND
CONTROL LOGIC
12
SIN
MUX
10-BIT DAC
ROM
MSB
DIVIDE
BY 2
MUX
AD9837
R
200Ω
FSYNC SCLK SDATA
Figure 1.
COMP
VOUT
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9837
TIMING CHARACTERISTICS
VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.
Table 2.
Parameter1
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
Limit at TMIN to TMAX
62.5
25
25
25
10
10
5
10
t4 − 5
5
3
5
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
Description
MCLK period (fMCLK = 16 MHz)
MCLK high duration (fMCLK = 16 MHz)
MCLK low duration (fMCLK = 16 MHz)
SCLK period
SCLK high duration
SCLK low duration
FSYNC to SCLK falling edge setup time
SCLK falling edge to FSYNC rising edge time
Data setup time
Data hold time
SCLK high to FSYNC falling edge setup time
1 Guaranteed by design; not production tested.
Timing Diagrams
t1
MCLK
t2
t3
Figure 2. Master Clock
Data Sheet
SCLK
FSYNC
t11
SDATA
t5
t7 t6
t4
t8
D15 D14
t10
t9
D2 D1
Figure 3. Serial Timing
D0
D15 D14
Rev. A | Page 4 of 28
5 Page 
AD9837
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale, a point 0.5 LSB
below the first code transition (000 … 00 to 000 … 01), and full
scale, a point 0.5 LSB above the last code transition (111 … 10
to 111 … 11). The error is expressed in LSBs.
Differential Nonlinearity (DNL)
DNL is the difference between the measured and ideal 1 LSB
change between two adjacent codes in the DAC. A specified
DNL of ±1 LSB maximum ensures monotonicity.
Output Compliance
Output compliance refers to the maximum voltage that can be
generated at the output of the DAC to meet the specifications.
When voltages greater than that specified for the output compli-
ance are generated, the AD9837 may not meet the specifications
listed in the data sheet.
Spurious-Free Dynamic Range (SFDR)
Along with the frequency of interest, harmonics of the funda-
mental frequency and images of these frequencies are present at
the output of a DDS device. The spurious-free dynamic range
(SFDR) refers to the largest spur or harmonic present in the
band of interest. The wideband SFDR gives the magnitude of
the largest spur or harmonic relative to the magnitude of the
fundamental frequency in the 0 to Nyquist bandwidth. The
narrow-band SFDR gives the attenuation of the largest spur or
harmonic in a bandwidth of ±200 kHz about the fundamental
frequency.
Data Sheet
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the rms value of the fundamental. For the AD9837,
THD is defined as
THD = 20 log
V22 + V32 + V4 2 + V52 + V62
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through sixth harmonics.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency. The value for SNR is expressed in decibels.
Clock Feedthrough
There is feedthrough from the MCLK input to the analog
output. Clock feedthrough refers to the magnitude of the
MCLK signal relative to the fundamental frequency in the
output spectrum of the AD9837.
Rev. A | Page 10 of 28
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet AD9837.PDF ] | |
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