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PDF DS1343 Data sheet ( Hoja de datos )

Número de pieza DS1343
Descripción (DS1343 / DS1344) Low-Current SPI/3-Wire RTCs
Fabricantes Maxim Integrated Products 
Logotipo Maxim Integrated Products Logotipo



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19-5801; Rev 0; 3/11
Low-Current SPI/3-Wire RTCs
General Description
The DS1343/DS1344 low-current real-time clocks (RTCs)
are timekeeping devices that provide an extremely low
standby current, permitting longer life from a backup
supply source. The devices also support high-ESR
crystals, broadening the pool of usable crystals for the
devices. The clock/calendar provides seconds, minutes,
hours, day, date, month, and year information. The date
at the end of the month is automatically adjusted for
months with fewer than 31 days, including corrections
for leap year. The clock operates in either 24-hour or
12-hour format with an AM/PM indicator.
Address and data are transferred serially through an
SPI™ or 3-wire interface. Two programmable time-of-day
alarms are provided. Each alarm can generate an inter-
rupt on a combination of seconds, minutes, hours, and
day. Don’t-care states can be inserted into one or more
fields if it is desired for them to be ignored for the alarm
condition. The time-of-day alarms can be programmed
to assert two different interrupt outputs, or they can be
combined to assert one common interrupt output. Both
interrupt outputs operate when the device is powered by
either VCC or VBAT.
The devices are available in a lead-free/RoHS-compliant,
20-pin TSSOP or 14-pin TDFN package, and support a
-40°C to +85°C extended industrial temperature range.
Medical
Handheld Devices
Telematicswww.DataSheet4U.net
Embedded Timestamping
Applications
Ordering Information appears at end of data sheet.
Features
S Low Timekeeping Current of 250nA (typ)
S Compatible with Crystal ESR Up to 100kI
S Versions Available to Support Either 6pF or
12.5pF Crystals
S RTC Counts Seconds, Minutes, Hours, Day, Date,
Month, and Year with Leap Year Compensation
Valid Through 2099
S Power-Fail and Switch Circuitry
S Three Operating Voltages
1.8V ±5%
3.0V±10%
3.3V ±10%
S Trickle-Charge Capability
S Maintain Time Down to 1.15V (typ)
S Support Motorola SPI Modes 1 and 3, or Standard
3-Wire Interface
S Burst Mode for Reading/Writing Successive
Addresses in Clock/RAM
S 96-Byte Battery-Backed NV RAM for Data Storage
S Two Time-of-Day Alarms with Two Interrupt
Outputs
S Industrial Temperature Range
S 20-Pin TSSOP or 14-Pin TDFN Package
Typical Operating Circuit
VCC
RPU
INT
RST
μP
3-WIRE
PORT
VCC
INT0
PF
INT1
CE
SCLK
SDI
SDO
DS1343
DS1344
X1
X2
VBAT
SERMODE GND
NOTE: SHOWN IN 3-WIRE I/O CONFIGURATION.
SPI is a trademark of Motorola, Inc.
________________________________________________________________ Maxim Integrated Products   1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

1 page




DS1343 pdf
Low-Current SPI/3-Wire RTCs
CE
tCC
SCLK*
SDI
tCDH
tDC
R/W = 1
tCL
A6
tF
tCH
tR
SPI Write Timing
tCWH
tCCH
tCDH
A0 D7 D0
WRITE ADDRESS BYTE
*SCLK CAN BE EITHER POLARITY. TIMING SHOWN FOR CPOL = 1.
SERMODE = VCC.
WRITE DATA BYTE
CE
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tCC
SCLK*
SDI
tCDH
tDC
R/W = 0
tCL
A6
SDO
tCH
A0
WRITE ADDRESS BYTE
*SCLK CAN BE EITHER POLARITY. TIMING SHOWN FOR CPOL = 1.
SERMODE = VCC.
SPI Read Timing
tCWH
tCDD tCDZ
D7 D0
READ DATA BYTE
5

5 Page





DS1343 arduino
Low-Current SPI/3-Wire RTCs
LOCAL GROUND PLANE (LAYER 2)
CRYSTAL
X1
X2
Figure 1. Layout Example
NOTE: AVOID ROUTING SIGNAL LINES
IN THE CROSSHATCHED AREA
(UPPER LEFT QUADRANT) OF
THE PACKAGE UNLESS THERE IS
A GROUND PLANE BETWEEN THE
SIGNAL LINE AND THE DEVICE PACKAGE.
Register Map
Table 1 shows the devices’ register map. During a mul-
tibyte RTC access, if the address pointer reaches the
end of the register space (1Fh), it wraps around to loca-
tion 00h. During a multibyte RAM access, if the address
pointer reaches the end of the register space (7Fh), it
wraps around to location 20h. On either the rising edge
of CE or an RTC address pointer wrap around, the cur-
rent time is transferred to a secondary set of registers.
The time information is read from these secondary regis-
ters, while the clock continues to run. This eliminates the
need to reread the registers in case the main registers
update during a read.
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Clock and Calendar (00h–06h)
The time and calendar information is obtained by reading
the appropriate register bytes. Table 1 shows the RTC
registers. The time and calendar are set or initialized by
writing the appropriate register bytes. The contents of
the time and calendar registers are in the BCD format.
The Day register increments at midnight and rolls over
from 7 to 1. Values that correspond to the day-of-week
are user defined, but must be sequential (i.e., if 1 equals
Sunday, then 2 equals Monday, and so on). Illogical time
and date entries result in undefined operation.
The devices can be run in either 12-hour or 24-hour
mode. Bit 6 of the Hours register is defined as the 12- or
24-hour mode-select bit. When high, the 12-hour mode
is selected. In the 12-hour mode, bit 5 is the AM/PM bit,
with a content of 1 being PM. In the 24-hour mode, bit 5
is the 20-hour field. Changing the 12/24 mode-select bit
requires that the Hours data subsequently be reentered,
including the Alarm register (if used). The Century bit (bit
GND
7 of Month) is toggled when the Years register rolls over
from 99 to 00. On a power-on reset (POR), the time and
date are set to 00:00:00 01/01/00 (hh:mm:ss MM/DD/YY),
and the Day register is set to 01.
Alarms (07h–0Eh)
The devices contains two time-of-day/date alarms. Alarm
0 can be set by writing to registers 07h–0Ah. Alarm 1 can
be set by writing to registers 0Bh–0Eh. The alarms can
be programmed to activate the INT0 or INT1 outputs on
an alarm match condition (see Table 2). Bit 7 of each
of the time of day/date alarm registers are mask bits.
When all the mask bits for each alarm are 0, an alarm
only occurs when the values in the timekeeping registers
00h–06h match the values stored in the alarm registers.
The alarms can also be programmed to repeat every
second, minute, hour, or day. Configurations not listed
in the table result in illogical operation. POR values are
undefined.
When the RTC register values match alarm register
settings, the corresponding alarm flag bit (IRQF0 or
IRQF1) is set to 1 in the Status register. If the corre-
sponding alarm interrupt enable bit (A0IE or A1IE) is
also set to 1 in the Control register, the alarm condition
activates the output(s) defined by the INTCN bit. Upon
an active alarm, clearing the associated IRQF[1:0] bit
deasserts the selected interrupt output while leaving
the alarm enabled for the next occurrence of a match.
Alternatively, clearing the A_IE bit deasserts the output
and inhibits further output activations.
The alarm flags are always active, fully independent of
the A_IE bit states. All alarm registers should be written
to logic zero to disable the alarm matching.
11

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