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71M6543F Schematic ( PDF Datasheet ) - Teridian Semiconductor

Teilenummer 71M6543F
Beschreibung Energy Meter ICs
Hersteller Teridian Semiconductor
Logo Teridian Semiconductor Logo 




Gesamt 30 Seiten
71M6543F Datasheet, Funktion
A Maxim Integrated Products Brand
19-5375; Rev 1.2; 4/11
71M6543F/H and 71M6543G/GH
Energy Meter ICs
DATA SHEET
April 2011
GENERAL DESCRIPTION
FEATURES
The 71M6543F, 71M6543H, 71M6543G, and 71M6543GH are
Teridian’s 4th-generation polyphase metering systems-on-chips
(SoCs) with a 5MHz 8051-compatible MPU core, low-power real-
time clock (RTC) with digital temperature compensation, flash
memory, and LCD driver. Our Single Converter Technology® with
a 22-bit delta-sigma ADC, seven analog inputs, digital metrology
temperature compensation, precision voltage reference, and a 32-
bit computation engine (CE) supports a wide range of metering
applications with very few external components.
The 71M6543F, 71M6543H, 71M6543G and 71M6543GH support
optional interfaces to the 71M6xx3 series of isolated sensors that
offer BOM cost reduction, immunity to magnetic tamper, and
enhanced reliability. The ICs feature ultra-low-power operation in
active and battery modes, 5KB shared RAM, and 64KB
(71M6543F, 71M6543H) or 128KB (71M6543G, 71M6543GH) of
flash memory, which can be programmed with code and/or data
during meter operation. High processing and sampling rates
combined with differential inputs offer a powerful metering platform
for commercial and industrial meters with up to class 0.2 accuracy
(71M6543H, 71M6543GH).
A complete array of code development tools, demonstration code,
and reference designs enable rapid development and certification of
meters that meet all ANSI and IEC electricity metering standards
worldwide.
0.1% Accuracy Over 2000:1 Current Range
Exceeds IEC 62053/ANSI C12.20 Standards
Seven Sensor Inputs with Neutral Current
Measurement, Differential Mode Selectable
for Current Inputs
Selectable Gain of 1 or 8 for One Current
Input to Support Shunts
High-Speed Wh/VARh Pulse Outputs with
Programmable Width
64KB Flash, 5KB RAM (71M6543F/H)
128KB Flash, 5KB RAM (71M6543G/GH)
Up to Four Pulse Outputs with Pulse Count
Four-Quadrant Metering, Phase Sequencing
Digital Temperature Compensation:
Metrology Compensation
Accurate RTC for TOU Functions with
Automatic Temperature Compensation
for Crystal in All Power Modes
Independent 32-Bit Compute Engine
46-64Hz Line Frequency Range with the Same
Calibration
Shunt Current Sensors
C
NEUTRAL
B
A
LOAD
www.DataSheet4U.net
POWER SUPPLY
NEUTRAL
Note: This system is referenced to Neutral
3x TERIDIAN
71M6xx3
Pulse Transformers
AMR
IR
HOST
MUX and ADC
IADC0
IADC1
}IN*
VADC10 (VC)
IADC6
IADC7
}IC
VADC9 (VB)
IADC4
IADC5
}IB
VADC8 (VA)
IADC2
IADC3
}IA
V3P3A V3P3SYS GNDA GNDD
TERIDIAN
PWR MODE
CONTROL
71M6543F/ WAKE-UP
71M6543H/ REGULATOR
71M6543G/
VBAT
71M6543GH VBAT_RTC
TEMPERATURE BATTERY
SENSOR
MONITOR
VREF
SERIAL PORTS
TX
RX
MODUL- RX
ATOR TX
POWER FAULT
COMPARATOR
SPI INTERFACE
RAM
COMPUTE
ENGINE
FLASH
MEMORY
MPU
RTC
TIMERS
ICE
COM0...5
SEG
SEG/DIO
LCD DRIVER
DIO, PULSES
DIO
V3P3D
OSCILLATOR/
PLL XIN
XOUT
*IN = Neutral Current
9/17/2010
BATTERY
RTC
BATTERY
LCD DISPLAY
8888.8888
PULSES,
DIO
I2C or µWire
EEPROM
32 kHz
Single Converter Technology is a registered trademark of Maxim Integrated
Products, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Phase Compensation (±7°)
Three Battery-Backup Modes:
Brownout Mode
LCD Mode
Sleep Mode
Wake-Up on Pin Events and Wake-on-Timer
1µA in Sleep Mode
Flash Security
In-System Program Update
8-Bit MPU (80515), Up to 5MIPS
Full-Speed MPU Clock in Brownout Mode
LCD Driver:
6 Common Segment Drivers
Up to 56 Selectable Pins
Up to 51 Multifunction DIO Pins
Hardware Watchdog Timer (WDT)
I2C/MICROWIRE™ EEPROM Interface
SPI Interface with Flash Program Capability
Two UARTs for IR and AMR
IR LED Driver with Modulation
Industrial Temperature Range
100-Pin Lead-Free LQFP Package
v1.2 © 2008–2011 Teridian Semiconductor Corporation 1






71M6543F Datasheet, Funktion
71M6543F/H and 71M6543G/GH Data Sheet
Tables
Table 1. Required CE Code and Settings for 1-Local / 3-Remotes ......................................................... 15
Table 2. Required CE Code and Settings for CT Sensors ...................................................................... 16
Table 3: Multiplexer and ADC Configuration Bits.................................................................................... 19
Table 4. RCMD[4:0] Bits ........................................................................................................................ 23
Table 5: Remote Interface Read Commands ......................................................................................... 23
Table 6: I/O RAM Control Bits for Isolated Sensor.................................................................................. 24
Table 7: Inputs Selected in Multiplexer Cycles ....................................................................................... 26
Table 8: CKMPU Clock Frequencies...................................................................................................... 30
Table 9: Memory Map............................................................................................................................ 31
Table 10: Internal Data Memory Map ..................................................................................................... 32
Table 11: Special Function Register Map............................................................................................... 32
Table 12: Generic 80515 SFRs - Location and Reset Values ................................................................. 33
Table 13: PSW Bit Functions (SFR 0xD0) ............................................................................................... 34
Table 14: Port Registers (SEGDIO0-15) ................................................................................................ 35
Table 15: Stretch Memory Cycle Width .................................................................................................. 35
Table 16. 80515 PCON SFR Register (SFR 0x87).................................................................................... 36
Table 17: Baud Rate Generation............................................................................................................ 36
Table 18: UART Modes ......................................................................................................................... 37
Table 19: The S0CON (UART0) Register (SFR 0x98) ............................................................................. 37
Table 20: The S1CON (UART1) Register (SFR 0x9B)............................................................................. 38
Table 21: PCON Register Bit Description (SFR 0x87).............................................................................. 38
Table 22: Timers/Counters Mode Description ........................................................................................ 39
Table 23: Allowed Timer/Counter Mode Combinations........................................................................... 39
Table 24: TMOD Register Bit Description (SFR 0x89) ............................................................................ 39
Table 25: The TCON Register Bit Functions (SFR 0x88) ........................................................................ 40
Table 26: The IEN0 Bit Functions (SFR 0xA8)........................................................................................ 41
Table 27: The IEN1 Bit Functions (SFR 0xB8)........................................................................................ 41
Table 28: The IEN2 Bit Functions (SFR 0x9A)........................................................................................ 41
Table 29: TCON Bit Functions (SFR 0x88) ............................................................................................. 41
Table 30: The T2CON Bit Functions (SFR 0xC8) .................................................................................... 42
Table 31: The IRCON Bit Functions (SFR 0xC0) .................................................................................... 42
Table 32: External MPU Interrupts ......................................................................................................... 42
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Table 33: Interrupt Enable and Flag Bits ................................................................................................ 43
Table 34: Interrupt Priority Level Groups................................................................................................ 43
Table 35: Interrupt Priority Levels .......................................................................................................... 44
Table 36: Interrupt Priority Registers (IP0 and IP1)................................................................................. 44
Table 37: Interrupt Polling Sequence ..................................................................................................... 45
Table 38: Interrupt Vectors .................................................................................................................... 45
Table 39: Flash Memory Access ............................................................................................................ 47
Table 40: Bank Switching with FL_BANK[1:0] (SFR 0xB6[1:0])in the 71M6543G/GH ............................... 48
Table 41: Flash Security ........................................................................................................................ 49
Table 42: Clock System Summary ......................................................................................................... 51
Table 43: RTC Control Registers ........................................................................................................... 52
Table 44: I/O RAM Registers for RTC Temperature Compensation........................................................ 53
Table 45: NV RAM Table Structure............................................................Error! Bookmark not defined.
Table 46: I/O RAM Registers for RTC Interrupts .................................................................................... 55
Table 47: I/O RAM Registers for Temperature and Battery Measurement .............................................. 56
Table 48: Selectable Resources using the DIO_Rn[2:0] Bits................................................................... 59
6
© 2008–2011 Teridian Semiconductor Corporation
v1.2

6 Page









71M6543F pdf, datenblatt
71M6543F/H and 71M6543G/GH Data Sheet
number of LCD segments and DIO pins can be implemented in software to accommodate various
requirements.
In addition to the temperature-trimmed ultra-precision voltage reference, the on-chip digital temperature
compensation mechanism includes a temperature sensor and associated controls for correction of unwanted
temperature effects on metrology and RTC accuracy (i.e., to meet the requirements of ANSI and IEC
standards). Temperature-dependent external components such as the crystal oscillator, current
transformers (CTs), Current Shunts and their corresponding signal conditioning circuits can be character-
ized and their correction factors can be programmed to produce electricity meters with exceptional accuracy
over the industrial temperature range.
One of the two internal UARTs is adapted to support an Infrared LED with internal drive and sense
configuration and can also function as a standard UART. The optical output can be modulated at 38 kHz.
This flexibility makes it possible to implement AMR meters with an IR interface. A block diagram of the IC
is shown in Figure 1.
2.2 Analog Front-End (AFE)
The AFE functions as a data acquisition system, controlled by the MPU. The 71M6543 AFE may also be
augmented by isolated 71M6xx3 sensors in order to support low-cost current shunt sensors. Figure 2,
and Figure 3 show the two most common configurations; other configurations are possible. Sensors that
are connected directly to the 71M6543 (i.e., IADC0-IADC1, VADC8, VADC9 and VADC10) are
multiplexed into the single second-order sigma-delta ADC input for sampling in the 71M6543. The
71M6543 ADC output is decimated by the FIR filter and stored in CE RAM where it can be accessed and
processed by the CE.
Shunt current sensors that are isolated by using a 71M6xx3 device, are sampled by a second-order
sigma delta ADC in the 71M6xx3 and the signal samples are transferred over the digital isolation interface
through the low-cost isolation pulse transformer.
Figure 2 shows the 71M6543 using shunt current sensors and the 71M6xx3 isolated sensor devices.
Figure 2 supports neutral current measurement with a local shunt connected to the IADC0-IADC1 input
plus three remote (isolated) shunt sensors. As seen in Figure 2, when a remote isolated shunt sensor is
connected via the 71M6xx3, the samples associated with this current channel are not routed to the
multiplexer, and are instead transferred digitally to the 71M6543 via the isolation interface and are directly
stored in CE RAM. The MUX_SELn[3:0] I/O RAM control fields allow the MPU to configure the AFE for the
desired multiplexer sampling sequence. Refer to Table 1 and Table 2 for the appropriate CE code and the
corresponding AFE settings.
See Figure 31 for the meter wiring configuration corresponding to Figure 2.
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IN*
Local
Shunt
IA
Remote
Shunt
INP
INN
71M6xx3
SP
SN
IB
Remote
Shunt
INP
INN
71M6xx3
SP
SN
IC
Remote
Shunt
INP
INN
71M6xx3
SP
SN
IADC0
IADC1
VADC8 (VA)
VADC9 (VB)
VADC10 (VC)
IADC2
IADC3
IADC4
IADC5
IADC6
IADC7
MUX
VREF
VREF
VADC
∆Σ ADC
CONVERTER
VREF
FIR
22
Digital
Isolation
Interface
22
CE RAM
22
22
*IN = Neutral Current
71M6543
9/17/2010
Figure 2: AFE Block Diagram (Shunts: One-Local, Three-Remotes)
12
© 2008–2011 Teridian Semiconductor Corporation
v1.2

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