A3PE600 Datasheet PDF - Actel Corporation
| Part Number | A3PE600 | |
| Description | ProASIC3E Flash Family FPGAs | |
| Manufacturers | Actel Corporation | |
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v1.0
ProASIC3E Flash Family FPGAs
with Optional Soft ARM® Support
®
Features and Benefits
High Capacity
• 600 k to 3 Million System Gates
• 108 to 504 kbits of True Dual-Port SRAM
• Up to 620 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
On-Chip User Nonvolatile Memory
• 1 kbit of FlashROM with Synchronous Interfacing
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock® to Secure FPGA Contents
Low Power
• Core Voltage for Low Power
• Support for 1.5-V-Only Systems
• Low-Impedance Flash Switches
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• Ultra-Fast Local and Long-Line Network
• Enhanced High-Speed, Very-Long-Line Network
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization
Pro (Professional) I/O
• 700 Mbps DDR, LVDS-Capable I/Os
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 8 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS
2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS
• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
Class I and II
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os
• Programmable Output Slew Rate and Drive Strength
• Programmable Input Delay
• Schmitt Trigger Option on Single-Ended Inputs
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC®3E Family
Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks, Each with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay
Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 200 MHz)
SRAMs and FIFOs
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
• True Dual-Port SRAM (except ×18)
• 24 SRAM and FIFO Configurations with Synchronous
ARMO®pePrartoiocneuspsotor
350 MHz
Support
in
ProASIC3E
FPGAs
• M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available
with or without Debug
Table 1-1 • ProASIC3E Product Family
ProASIC3E Devices
Cortex-M1 Devices1
A3PE600
A3PE1500
M1A3PE1500
System Gates
600 k
1.5 M
VersaTiles (D-flip-flops)
RAM kbitswww.DataSheet4U.net (1,024 bits)
13,824
108
38,400
270
4,608-Bit Blocks
24 60
FlashROM Bits
1k 1k
Secure (AES) ISP
CCCs with Integrated PLLs2
VersaNet Globals3
Yes
6
18
Yes
6
18
I/O Banks
88
Maximum User I/Os
270 444
Package Pins
PQFP
FBGA
PQ208
FG256, FG484
PQ208
FG484, FG676
Notes:
1. Refer to the Cortex-M1 product brief for more information.
2. The PQ208 package has six CCCs and two PLLs.
3. Six chip (main) and three quadrant global networks are available.
4. For devices supporting lower densities, refer to the ProASIC3 Flash Family FPGAs handbook.
A3PE3000
M1A3PE3000
3M
75,264
504
112
1k
Yes
6
18
8
620
PQ208
FG324, FG484, FG896
March 2008
© 2008 Actel Corporation
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1 – ProASIC3E Device Family Overview
General Description
ProASIC3E, the third-generation family of Actel flash FPGAs, offers performance, density, and
features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3E
devices the advantage of being a secure, low-power, single-chip solution that is live at power-up
(LAPU). ProASIC3E is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost.
These features enable designers to create high-density systems using existing ASIC or FPGA design
flows and tools.
ProASIC3E devices offer 1 kbit of on-chip, programmable, nonvolatile FlashROM storage as well as
clock conditioning circuitry based on six integrated phase-locked loops (PLLs). ProASIC3E devices
have up to three million system gates, supported with up to 504 kbits of true dual-port SRAM and
up to 620 user I/Os.
Several ProASIC3E devices support the Cortex-M1 soft IP cores, and the ARM-Enabled devices have
Actel ordering numbers that begin with M1A3PE.
www.DataSheet4U.net
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike
SRAM-based FPGAs, flash-based ProASIC3E devices allow all functionality to be live at power-up; no
external boot PROM is required. On-board security mechanisms prevent access to all the
programming information and enable secure remote updates of the FPGA logic. Designers can
perform secure remote in-system reprogramming to support future design iterations and field
upgrades with confidence that valuable intellectual property (IP) cannot be compromised or
copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3E
family device architecture mitigates the need for ASIC migration at higher user volumes. This
makes the ProASIC3E family a cost-effective ASIC replacement solution, especially for applications
in the consumer, networking/ communications, computing, and avionics markets.
Security
The nonvolatile, flash-based ProASIC3E devices do not require a boot PROM, so there is no
vulnerable external bitstream that can be easily copied. ProASIC3E devices incorporate FlashLock,
which provides a unique combination of reprogrammability and design security without external
overhead, advantages that only an FPGA with nonvolatile flash programming can offer.
ProASIC3E devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed
intellectual property and configuration data. In addition, all FlashROM data in ProASIC3E devices
can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher
encryption standard. The AES standard was adopted by the National Institute of Standards and
Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3E devices have a built-in
AES decryption engine and a flash-based AES key that make them the most comprehensive
programmable logic device security solution available today. ProASIC3E devices with AES-based
security allow for secure, remote field updates over public networks such as the Internet, and
ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP
thieves. The contents of a programmed ProASIC3E device cannot be read back, although secure
design verification is possible.
Security, built into the FPGA fabric, is an inherent component of the ProASIC3E family. The flash
cells are located beneath seven metal layers, and many device design and layout techniques have
been used to make invasive attacks extremely difficult. The ProASIC3E family, with FlashLock and
AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your
v1.0
1-1
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| Information | Total 70 Pages | |
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| Download | [ A3PE600.PDF Datasheet ] | |
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