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AD8391 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD8391
Beschreibung xDSL Line Driver
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD8391 Datasheet, Funktion
a
FEATURES
Ideal xDSL Line Driver for VoDSL or Low Power
Applications such as USB, PCMCIA, or PCI Based
Customer Premise Equipment (CPE)
High Output Voltage and Current Drive
340 mA Output Drive Current
Low Power Operation
3 V to 12 V Power Supply Range
1-Pin Logic Controlled Standby, Shutdown
Low Supply Current of 19 mA (Typical)
Low Distortion
–82 dBc SFDR, 12 V p-p into Differential 21 @ 100 kHz
4.5 nV/Hz Input Voltage Noise Density, 100 kHz
Out-of-Band SFDR = –72 dBc, 144 kHz to 500 kHz,
ZLINE = 100 , PLINE = 13.5 dBm
High Speed
40 MHz Bandwidth (–3 dB)
375 V/s Slew Rate
APPLICATIONS
VoDSL Modems
xDSL USB, PCI, PCMCIA Cards
Line Powered or Battery Backup xDSL Modems
xDSL Line Driver
3 V to 12 V with Power-Down
AD8391
PIN CONFIGURATION
8-Lead SOIC
(Thermal Coastline)
IN1 1
PWDN 2
+VS 3
VOUT1 4
؊VS
VMID
؉VS
؊؉
؉؊
AD8391
8 IN2
7 VMID
6 –VS
5 VOUT2
PRODUCT DESCRIPTION
The AD8391 consists of two parallel, low cost xDSL line drive
amplifiers capable of driving low distortion signals while running on
both 3 V to 12 V single-supply or equivalent dual-supply rails. It is
primarily intended for use in single-supply xDSL systems where low
power is essential, such as line powered and battery backup systems.
Each amplifier output drives more than 250 mA of current while
maintaining 82 dBc of SFDR at 100 kHz on 12 V, outstanding
performance for any xDSL CPE application.
The AD8391 provides a flexible power-down feature consisting of
a 1-pin digital control line. This allows biasing of the AD8391 to
full power (Logic 1), standby (Logic three-state maintains low
amplifier output impedance), and shutdown (Logic 0 places
amplifier outputs in a high impedance state). PWDN is refer-
enced to VS.
Fabricated on ADIs high speed XFCB process, the high bandwidth
and fast slew rate of the AD8391 keep distortion to a minimum,
while dissipating a minimum of power. The quiescent current of the
AD8391 is low: 19 mA total static current draw. The AD8391
comes in a compact 8-lead SOIC thermal coastlinepackage and
operates over the temperature range 40°C to +85°C.
EMPTY BIN
25
137.5
250
FREQUENCY – kHz
Figure 1. Upstream Transit Spectrum with Empty Bin
at 45 kHz; Line Power = 12.5 dBm into 100
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.






AD8391 Datasheet, Funktion
AD8391
12
9 VS = ؎6V
RL = 10
6 G = –2
3
0
–3
–6
–9
–12
–15
–18
0.1
1 10 100
FREQUENCY – MHz
1000
TPC 7. Output Voltage vs. Frequency
1500
1250
1000
VS = ؎6V
VOH @+85؇C
VOH @+25؇C
VOH @–40؇C
750
500
VOL @+85؇C
250 VOL @+25؇C
VOL @–40؇C
0
0 100 200 300 400 500 600 700 800 900 1000
LOAD CURRENT – mA
TPC 8. Output Saturation Voltage vs. Load
18
15
12
STANDBY
9
VS = ؎6V
RL = 10
G = ؊2
6
3
0 FULL POWER
–3
–6
–9
0.1
1 10 100
FREQUENCY – MHz
1000
TPC 9. Small Signal Frequency Response
6
3 VS = ؎1.5V
RL = 10
0 G = –2
–3
–6
–9
–12
–15
–18
–21
–24
0.1
1 10 100
FREQUENCY – MHz
1000
TPC 10. Output Voltage vs. Frequency
1200
1000
800
VS = ؎1.5V
VOH @+85؇C
VOH @+25؇C
VOH @–40؇C
VOL@ –40؇C
600
400
200
0
0
VOL@ +25؇C
VOL@+ 85؇C
50 100 150 200 250 300 350 400 450 500
LOAD CURRENT – mA
TPC 11. Output Saturation Voltage vs. Load
18
15
VS = ؎1.5V
RL = 10
G = ؊2
12
STANDBY
9
6
3
0 FULL POWER
–3
–6
–9
0.1
1 10 100
FREQUENCY – MHz
1000
TPC 12. Small Signal Frequency Response
6REV. A

6 Page









AD8391 pdf, datenblatt
AD8391
Using these calculations and a θJA of 100°C/W for the SOIC,
Table II shows junction temperature versus power delivered to
the line for several supply voltages while operating at an ambient
temperature of 85°C. Operation at a junction temperature over
the absolute maximum rating of 150°C should be avoided.
Table II. Junction Temperature vs. Line Power
and Operating Voltage for SOIC at 85؇C Ambient
VSUPPLY
PLINE, dBm
13
14
15
12 12.5
125 126
127 129
129 131
Thermal stitching, which connects the outer layers to the internal
ground plane(s), can help to use the thermal mass of the PCB to
draw heat away from the line driver and other active components.
Layout Considerations
As is the case with all high speed applications, careful attention
to printed circuit board layout details will prevent associated
board parasitics from becoming problematic. Proper RF design
techniques are mandatory. The PCB should have a ground plane
covering all unused portions of the component side of the board
to provide a low impedance return path. Removing the ground
plane on all layers from the areas near the input and output pins
will reduce stray capacitance, particularly in the area of the
inverting inputs. The signal routing should be short and direct in
order to minimize parasitic inductance and capacitance associated
with these traces. Termination resistors and loads should be located
as close as possible to their respective inputs and outputs.
Input and output traces should be kept as far apart as possible
to minimize coupling (crosstalk) through the board. Wherever
there are complementary signals, a symmetrical layout should be
provided to the extent possible to maximize balanced perfor-
mance. When running differential signals over a long distance, the
traces on the PCB should be close. This will reduce the radiated
energy and make the circuit less susceptible to RF interference.
Adherence to stripline design techniques for long signal traces
(greater than about one inch) is recommended.
+ 453909
1F
0.1F
876
12.5
5
1:2
+VS
VIN VMID AD8391
–VS
RL
1 2 34
+3V
– 453909
+–
12.5
1F
0.1F
10F
+
VCC
Figure 6. Single-Supply Voltage Differential Drive Circuit
Evaluation Board
The AD8391 is available installed on an evaluation board.
Figure 10 shows the schematics for the evaluation board. AC-
coupling capacitors of 0.1 µF, C6 and C11, in combination with
10 k, resistors R25 and R26, will form a first-order high-pass
pole at 160 Hz.
The bill of materials included as Table III represents the com-
ponents that are installed in the evaluation board when it is
shipped to a customer. There are footprints for additional components,
such as an AD8138, that will convert a single-ended signal into a
differential signal. There is also a place for an AD9632, which can
be used to convert a differential signal into a single-ended signal.
Transformer Selection
Customer premise ADSL requires the transmission of a 13 dBm
(20 mW) DMT signal. The DMT signal has a crest factor of 5.3,
requiring the line driver to provide peak line power of 560 mW.
560 mW peak line power translates into a 7.5 V peak voltage on a
100 telephone line. Assuming that the maximum low distortion
output swing available from the AD8391 line driver on a 12 V
supply is 11 V, and taking into account the power lost due to the
termination resistance, a step-up transformer with a turns ratio
of 1:2 is adequate for most applications. If the modem designer
desires to transmit more than 13 dBm down the twisted pair, a
higher turns ratio can be used for the transformer. This trade-off
comes at the expense of higher power dissipation by the line
driver as well as increased attenuation of the downstream signal
that is received by the transceiver.
In the simplified differential drive circuit shown in Figure 6, the
AD8391 is coupled to the phone line through a step-up transformer
with a 1:2 turns ratio. R45 and R46 are back termination or line
matching resistors, each 12.5 [1/2 (100 /22 )] where 100 is
the approximate phone line impedance. A transformer reflects
impedance from the line side to the IC side as a value inversely
proportional to the square of the turns ratio. The total differential
load for the AD8391, including the termination resistors, is 50 .
Even under these conditions, the AD8391 provides low distor-
tion signals to within 0.5 V of the power supply rails.
One must take care to minimize any capacitance present at the
outputs of a line driver. The sources of such capacitance can
include but are not limited to EMI suppression capacitors,
overvoltage protection devices, and the transformers used in the
hybrid. Transformers have two kinds of parasitic capacitances:
distributed or bulk capacitance and interwinding capacitance.
Distributed capacitance is a result of the capacitance created
between each adjacent winding on a transformer. Interwinding
capacitance is the capacitance that exists between the windings
on the primary and secondary sides of the transformer. The
existence of these capacitances is unavoidable and limiting both
distributed and interwinding capacitance to less than 20 pF each
should be sufficient for most applications.
It is also important that the transformer operates in its linear
region throughout the entire dynamic range of the driver.
Distortion introduced by the transformer can severely degrade
DSL performance, especially when operating at long loop lengths.
12
REV. A

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