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PDF ADP320 Data sheet ( Hoja de datos )

Número de pieza ADP320
Descripción High PSRR Voltage Regulator
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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FEATURES
Bias voltage range (VBIAS): 2.5 V to 5.5 V
LDO input voltage range (VIN1/VIN2, VIN3): 1.8 V to 5.5 V
Three 200 mA low dropout voltage regulators
16-lead, 3 mm × 3 mm LFCSP
Initial accuracy: ±1%
Stable with 1 μF ceramic output capacitors
No noise bypass capacitor required
3 independent logic controlled enables
Over current and thermal protection
Key specifications
High PSRR
76 dB PSRR up to 1 kHz
70 dB PSRR 10 kHz
60 dB PSRR at 100 kHz
40 dB PSRR at 1 MHz
Low output noise
29 μV rms typical output noise at VOUT = 1.2 V
55 μV rms typical output noise at VOUT = 2.8 V
Excellent transient response
Low dropout voltage: 110 mV @ 200 mA load
85 μA typical ground current at no load, all LDOs enabled
100 μs fast turn-on circuit
Guaranteed 200 mA output current per regulator
−40°C to +125°C junction temperature
APPLICATIONS
Mobile phones
Digital cameras and audio devices
Portable and battery-powered equipment
Portable medical devices
Post dc-to-dc regulation
GENERAL DESCRIPTION
The ADP320 200 mA triple output LDO combines high PSRR, low
noise, low quiescent current, and low dropout voltage in a voltage
regulator ideally suited for wireless applications with demanding
performance and board space requirements.
The low quiescent current, low dropout voltage, and wide input
voltage range of the ADP320 triple LDO extend the battery life of
portable devices. The ADP320 triple LDO maintains power supply
rejection greater than 60 dB for frequencies as high as 100 kHz
www.DwhatilaeSohpeeerta4tUin.gcowmith a low headroom voltage. The ADP320 triple
Triple, 200 mA, Low Noise,
High PSRR Voltage Regulator
ADP320
TYPICAL APPLICATION CIRCUITS
2.5V TO VBIAS
5.5V
+
1µF
ADP320 VBIAS
1.8V TO VIN1/VIN2
5.5V
+
1µF ON
EN1
OFF
LDO 1
EN LD1
VBIAS
1.8V TO VIN3
5.5V
ON
EN2
OFF
+
1µF ON
EN3
OFF
LDO 2
EN LD2
VBIAS
LDO 3
EN LD3
GND
VOUT1
+
1µF
VOUT2
+
1µF
VOUT3
+
1µF
Figure 1. Typical Application Circuit
LDO offers much lower noise performance than competing LDOs
without the need for a noise bypass capacitor.
The ADP320 triple LDO is available in a miniature 16-lead
3 mm × 3 mm LFCSP package and is stable with tiny 1 μF ±30%
ceramic output capacitors, resulting in the smallest possible board
area for a wide variety of portable power needs.
The ADP320 triple LDO is available in output voltage combin-
ations ranging from 0.8 V to 3.3 V and offers over current and
thermal protection to prevent damage in adverse conditions.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.

1 page




ADP320 pdf
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN1/VIN2, VIN3, VBIAS to GND
VOUT1, VOUT2 to GND
VOUT3 to GND
EN1, EN2, EN3 to GND
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
–0.3 V to +6.5 V
–0.3 V to VIN1/VIN2
–0.3 V to VIN3
–0.3 V to +6.5 V
–65°C to +150°C
–40°C to +125°C
JEDEC J-STD-020
Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination.
The ADP320 triple LDO can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temper-
ature does not guarantee that the junction temperature (TJ)
is within the specified temperature limits. In applications
with high power dissipation and poor thermal resistance the
maximum ambient temperature may have to be derated. In
applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits.
The junction temperature (TJ) of the device is dependent on
the ambient temperature (TA), the power dissipation of the
device (PD), and the junction-to-ambient thermal resistance of
the package (θJA). Maximum junction temperature (TJ) is
calculated from the ambient temperature (TA) and power dissi-
pation (PD) using the following formula:
TJ = TA + (PD × θJA)
ADP320
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a four-layer, 4-inch × 3-inch
circuit board. Refer to JEDEC JESD 51-9 for detailed informa-
tion on the board construction. For additional information, see
the AN-617 Application Note, MicroCSP™ Wafer Level Chip
Scale Package.
ΨJB is the junction to board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12, Guidelines
for Reporting and Using Package Thermal Information, states
that thermal characterization parameters are not the same as
thermal resistances. ΨJB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θJB. Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation
from the package; factors that make ΨJB more useful in real-
world applications. Maximum junction temperature (TJ) is
calculated from the board temperature (TB) and power
dissipation (PD) using the following formula
TJ = TB + (PD × ΨJB)
Refer to JEDEC JESD51-8 and JESD51-12 for more detailed
information about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4.
Package Type
16-Lead 3 mm × 3 mm LFCSP
θJA ΨJB Unit
49.5 25.2 °C/W
ESD CAUTION
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Rev. 0 | Page 5 of 20

5 Page





ADP320 arduino
160
140
120
100
80
60
40 LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
20 LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
0
1.70 1.80 1.90 2.00 2.10
VIN (V)
Figure 27. Ground Current vs. Input Voltage in Dropout), VOUT2 = 1.8 V
0
200mA
–10
100mA
10mA
1mA
–20
–30
VRIPPLE = 50mV
VIN = 2.8V
VOUT = 1.8V
COUT = 1µF
–40
–50
–60
–70
–80
–90
–100
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 28. Power Supply Rejection Ratio vs. Frequency, 1.8 V
0
200mA
–10
100mA
10mA
1mA
–20
VRIPPLE = 50mV
VIN = 4.3V
VOUT = 3.3V
COUT = 1µF
–30
–40
–50
–60
–70
–80
–90
–100
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
www.DataShFeiegtu4reU2.9c.oPmower Supply Rejection Ratio vs. Frequency, 3.3 V
ADP320
0
VRIPPLE = 50mV
–10 VIN = 2.5V
VOUT = 1.5V
–20 COUT = 1µF
200mA
100mA
10mA
1mA
–30
–40
–50
–60
–70
–80
–90
–100
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 30. Power Supply Rejection Ratio vs. Frequency, 1.5 V
0
1.8V/200mA
–10
1.8V/100mA
1.8V/10mA
1.2V/200mA
–20 1.2V/100mA
1.2V/10mA
–30
VRIPPLE = 50mV
1V HEADROOM
1.8V PSRR
1.2 XTALK
–40
–50
–60
–70
–80
–90
–100
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 31. Power Supply Rejection Ratio vs. Frequency,
Channel to Channel Crosstalk
10
3.3V
1.8V
1.5V
1
0.1
0.01
10 100 1k 10k 100k
FREQUENCY (Hz)
Figure 32. Output Noise Spectral Density, VIN = 5 V, ILOAD = 10 mA
Rev. 0 | Page 11 of 20

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