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PCA9525 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCA9525
Beschreibung Simple 2-wire bus buffer
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 22 Seiten
PCA9525 Datasheet, Funktion
PCA9525
Simple 2-wire bus buffer
Rev. 1 — 25 February 2011
Product data sheet
1. General description
The PCA9525 is a monolithic CMOS integrated circuit for bus buffering in applications
including I2C-bus, SMBus, DDC, PMBus, and other systems based on similar principles.
The buffer extends the bus load limit by buffering both the SCL and SDA lines, allowing
the maximum permissible bus capacitance on both sides of the buffer.
The PCA9525 includes a unidirectional buffer for the clock signal, and a bidirectional
buffer for the data signal. Slave devices which employ clock stretching are therefore not
supported.
In its most basic implementation, the buffer will allow an extended number of slave
devices to be attached to one (or more) master devices. In this case, all master devices
would be positioned on the Sxx_IN side of the PCA9525.
The direction pin (DIR) further enhances this function by allowing the unidirectional clock
signal to be reversed, thus allowing master devices on both sides of the buffer.
The enable (EN) function allows sections of the bus to be isolated. Individual parts of the
system can be brought on-line successively. This means a controlled start-up using a
diverse range of components, operating speeds and loads is easily achieved.
2. Features and benefits
„ Simple impedance isolating buffer for 2-wire buses
„ 4 mA maximum static open-drain pull-down capability supports a wide range of bus
standards
„ Works with I2C-bus (Standard-mode, Fast-mode), SMBus (standard and high power
mode), and PMBus
„ Fast switching times allow operation in excess of 1 MHz
„ Enable allows bus segments to be disconnected
„ Hysteresis on inputs provides noise immunity
„ Operating voltages from 2.7 V to 5.5 V
„ Very low supply current
„ Uncomplicated characteristics suitable for quick implementation in most common
2-wire bus applications
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PCA9525 Datasheet, Funktion
NXP Semiconductors
PCA9525
Simple 2-wire bus buffer
Table 4. Characteristics …continued
Tamb = 40 °C to +85 °C; voltages are specified with respect to ground (VSS); VDD = 5.5 V unless otherwise specified.
Symbol Parameter
Conditions
Min Typ Max
Unit
Enable (EN)
Vth(en)
enable threshold voltage
Vth(dis)
disable threshold voltage
Vhys hysteresis voltage
ILI input leakage current
Direction (DIR)
EN active; VDD = 2.7 V
EN active; VDD = 5.5 V
EN standby; VDD = 2.7 V
EN standby; VDD = 5.5 V
VDD = 2.7 V
VDD = 5.5 V
VI = VDD
2.0 -
4.8 -
--
--
100 -
200 -
--
-V
-V
0.9 V
2.1 V
- mV
- mV
±0.1 μA
VI(dir)
direction input voltage
direction SCL_OUT to SCL_IN
VDD = 2.7 V
VDD = 5.5 V
direction SCL_IN to SCL_OUT
2.0 -
4.8 -
-
-
V
V
Vhys hysteresis voltage
ILI input leakage current
Timing characteristics (Figure 4)
VDD = 2.7 V
VDD = 5.5 V
VDD = 2.7 V
VDD = 5.5 V
VI = VDD
--
--
100 -
200 -
--
0.9 V
2.1 V
- mV
- mV
±0.1 μA
td delay time
tf fall time
RPU = 620 Ω
RPU = 620 Ω
[1] -
[1] -
17 -
3.5 -
ns
ns
[1] Guaranteed by design, not subject to test.
[2] Supply voltage dependent; refer to graphs (Figure 5 through Figure 8) for typical trend.
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VI2C-bus
Fig 4. Timing diagram
70 % VDD
30 % VDD
30 % VDD
td
tf
Sxx_IN
Sxx_OUT
time
002aaf332
PCA9525
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
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PCA9525 pdf, datenblatt
NXP Semiconductors
PCA9525
Simple 2-wire bus buffer
5V
VDD
SCL
SDA
BUS MASTER
IRQ
U2
R1
MASTER/
SLAVE
U3
R2 R3 R4
VDD
SCL_IN SCL_OUT
SDA_IN SDA_OUT
EN
PCA9525
DIR
U1
master U4 requests SCL
direction change from
master U2 using IRQ
MASTER
SLAVE
U4 U5
SCL
SDA
002aaf343
Fig 15. PCA9525 with masters on both sides of buffer
Multiplexers such as the PCA9544A are simple analog switches which provide no
capacitive load isolation between connected branches. Figure 16 shows the PCA9525
enhancing an I2C-bus multiplexer application by isolating the load capacitance of each
branch. Figure 17 and Figure 18 show alternate forms of bus multiplexing, with the latter
being an excellent way to eliminate the requirement for a master to dedicate pins to
enabling multiple PCA9525 devices.
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3.3 V
R1
1.5 kΩ
VCC
SCL
SDA
BUS MASTER
U1
R2
1.5 kΩ
R3
1.1 kΩ
VDD
SCL_IN SCL_OUT
SDA_IN SDA_OUT
EN PCA9525
DIR
U2
R4
1.1 kΩ
VDD
SCL SC0
SDA
SD0
INT[3:0]
A0
A1
SC1
SD1
SC2
SD2
SC3
Using the PCA9525,
up to 400 pF may be
connected to each
and every bus 0
through bus 3.
A2 SD3
PCA9544A
U3
002aaf344
Alternately, using the PCA9546A, (which allows multiple outputs to be selected) you would simply
place a PCA9525 on each output on the right hand side, rather than a single PCA9525 on the
left hand side.
Fig 16. PCA9525 multiplexer isolation application
PCA9525
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 25 February 2011
© NXP B.V. 2011. All rights reserved.
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