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Teilenummer | AD9284 |
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Beschreibung | 1.8 V Dual Analog-to-Digital Converter (ADC) | |
Hersteller | Analog Devices | |
Logo | ||
Gesamt 25 Seiten Data Sheet
8-Bit, 250 MSPS, 1.8 V Dual
Analog-to-Digital Converter (ADC)
AD9284
FEATURES
GENERAL DESCRIPTION
Single 1.8 V supply operation
SNR: 49.3 dBFS at 200 MHz input at 250 MSPS
SFDR: 65 dBc at 200 MHz input at 250 MSPS
Low power: 314 mW at 250 MSPS
On-chip reference and track-and-hold
1.2 V p-p analog input range for each channel
Differential input with 500 MHz bandwidth
LVDS-compliant digital output
DNL: ±0.2 LSB
Serial port control options
Offset binary, Gray code, or twos complement data format
Optional clock duty cycle stabilizer
Built-in selectable digital test pattern generation
Pin-programmable power-down function
Available in 48-lead LFCSP
APPLICATIONS
Communications
Diversity radio systems
I/Q demodulation systems
Battery-powered instruments
Handheld scope meters
Low cost digital oscilloscopes
OTS: video over fiber
The AD9284 is a dual 8-bit, monolithic sampling, analog-to-digital
converter (ADC) that supports simultaneous operation and is
optimized for low cost, low power, and ease of use. Each ADC
operates at up to a 250 MSPS conversion rate with outstanding
dynamic performance.
The ADC requires a single 1.8 V supply and an encode clock for
full performance operation. No external reference components
are required for many applications. The digital outputs are LVDS
compatible.
The AD9284 is available in a Pb-free, 48-lead LFCSP that is
specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Integrated Dual 8-Bit, 250 MSPS ADC.
2. Single 1.8 V Supply Operation with LVDS Outputs.
3. Power-Down Option Controlled via a Pin-Programmable
Setting.
FUNCTIONAL BLOCK DIAGRAM
SDIO/
PWDN CSB SCLK
OE
CLK+
CLK–
VIN+A
VIN–A
VCM
VREF
1.0V
VREF
SPI
ADC
D7+ (MSB), D7– (MSB)
D0+ (LSB), D0– (LSB)
(CHANNEL A)
REF
SELECT
×1.5
CLOCK
MANAGEMENT
DCO
GENERATION
DCO+
DCO–
VIN–B
VIN+B
ADC
D7+ (MSB), D7– (MSB)
D0+ (LSB), D0– (LSB)
(CHANNEL B)
AD9284
RBIAS
AGND
AVDD DRVDD DRGND
Figure 1.
Rev. A
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Data Sheet
AD9284
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature, unless otherwise noted.
Table 3.
Parameter1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage2
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS
CSB
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
SCLK, SDIO/PWDN, OE
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS (D7+, D7− to D0+, D0−), LVDS
DRVDD = 1.8 V
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
Temperature Min
Full
Full 0.2
Full AVDD − 0.3
Full 1.2
Full 0
Full −10
Full −10
25°C
25°C
Typ
LVDS/PECL
1.2
20
4
Max
6
AVDD + 1.6
3.6
0.8
+10
+10
Unit
V
V p-p
V
V
V
μA
μA
kΩ
pF
Full 1.2
DRVDD + 0.3 V
Full 0
0.8 V
Full
−5
−0.4 +5
μA
Full −80 −63 −50 μA
25°C 30 kΩ
25°C 2 pF
Full 1.2
Full 0
Full 50
Full −5
25°C
25°C
DRVDD + 0.3 V
0.8 V
57 70 μA
−0.4 +5
μA
30 kΩ
2 pF
Full 290 345 400 mV
Full 1.15 1.25 1.35 V
Offset binary
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were
completed.
2 Specified for LVDS and LVPECL only.
Rev. A | Page 5 of 24
6 Page Data Sheet
75 50.0
70
SFDR: SIDE A
SFDR: SIDE B
65
SNRFS: SIDE A
60
SNRFS: SIDE B
55
49.8
49.6
49.4
49.2
50
50
49.0
75 100 125 150 175 200 225 250
ENCODE (MSPS)
Figure 10. SNRFS/SFDR vs Encode with fIN = 2.4 MHz
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
0
32 64 96 128 160 192
OUTPUT CODE
Figure 11. DNL Error with fIN = 4.3 MHz
224
256
AD9284
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
0
32 64 96 128 160 192
OUTPUT CODE
Figure 12. INL Error with fIN = 4.3 MHz
224
256
Rev. A | Page 11 of 24
12 Page | ||
Seiten | Gesamt 25 Seiten | |
PDF Download | [ AD9284 Schematic.PDF ] |
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