|
|
PDF AD9739A Data sheet ( Hoja de datos )
| Número de pieza | AD9739A | |
| Descripción | RF Digital-to-Analog Converters | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD9739A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Data Sheet
11-/14-Bit, 2.5 GSPS,
RF Digital-to-Analog Converters
AD9737A/AD9739A
FEATURES
Direct RF synthesis at 2.5 GSPS update rate
DC to 1.25 GHz in baseband mode
1.25 GHz to 3.0 GHz in mix-mode
Industry leading single/multicarrier IF or RF synthesis
Dual-port LVDS data interface
Up to 1.25 GSPS operation
Source synchronous DDR clocking
Pin compatible with the AD9739
Programmable output current: 8.7 mA to 31.7 mA
Low power: 1.1 W at 2.5 GSPS
APPLICATIONS
Broadband communications systems
DOCSIS CMTS systems
Military jammers
Instrumentation, automatic test equipment
Radar, avionics
SDIO
SDO
CS
SCLK
FUNCTIONAL BLOCK DIAGRAM
RESET
IRQ
AD9737A/AD9739A
1.2V
SPI
DAC BIAS
VREF
I120
IOUTN
DCI
TxDAC
CORE
IOUTP
DCO
CLK DISTRIBUTION
(DIV-BY-4)
DLL
(MU CONTROLLER)
GENERAL DESCRIPTION
The AD9737A/AD9739A are 11-bit and 14-bit, 2.5 GSPS high
performance RF DACs that are capable of synthesizing wideband
signals from dc up to 3 GHz. The AD9737A/AD9739A are pin
and functionally compatible with the AD9739 with the
exception that the AD9737A/AD9739A do not support
synchronization or RZ mode, and are specified to operate
between 1.6 GSPS and 2.5 GSPS.
By elimination of the synchronization circuitry, some nonideal
artifacts such as images and discrete clock spurs remain stationary
on the AD9737A/AD9739A between power-up cycles, thus
allowing for possible system calibration. AC linearity and noise
performance remain the same between the AD9739 and the
AD9737A/AD9739A.
The inclusion of on-chip controllers simplifies system integration.
A dual-port, source synchronous, LVDS interface simplifies the
digital interface with existing FGPA/ASIC technology. On-chip
controllers are used to manage external and internal clock domain
variations over temperature to ensure reliable data transfer from
the host to the DAC core. A serial peripheral interface (SPI) is
used for device configuration as well as readback of status
registers.
Figure 1.
DACCLK
The AD9737A/AD9739A are manufactured on a 0.18 µm
CMOS process and operate from 1.8 V and 3.3 V supplies.
They are supplied in a 160-ball chip scale ball grid array for
reduced package parasitics.
PRODUCT HIGHLIGHTS
1. Ability to synthesize high quality wideband signals with
bandwidths of up to 1.25 GHz in the first or second
Nyquist zone.
2. A proprietary quad-switch DAC architecture provides
exceptional ac linearity performance while enabling mix-
mode operation.
3. A dual-port, double data rate, LVDS interface supports the
maximum conversion rate of 2500 MSPS.
4. On-chip controllers manage external and internal clock
domain skews.
5. Programmable differential current output with an 8.66 mA
to 31.66 mA range.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011-2012 Analog Devices, Inc. All rights reserved.
1 page  
Data Sheet
AD9737A/AD9739A
LVDS DIGITAL SPECIFICATIONS
VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA. LVDS drivers and receivers are compliant to the IEEE Standard 1596.3-
1996 reduced range link, unless otherwise noted.
Table 2.
Parameter
LVDS DATA INPUTS (DB0[13:0], DB1[13:0])1
Input Common-Mode Voltage Range, VCOM
Logic High Differential Input Threshold, VIH_DTH
Logic Low Differential Input Threshold, VIL_DTH
Receiver Differential Input Impedance, RIN
Input Capacitance
LVDS Input Rate
LVDS Minimum Data Valid Period (tMDE) (See Figure 159)
LVDS CLOCK INPUT (DCI)2
Input Common-Mode Voltage Range, VCOM
Logic High Differential Input Threshold, VIH_DTH
Logic Low Differential Input Threshold, VIL_DTH
Receiver Differential Input Impedance, RIN
Input Capacitance
Maximum Clock Rate
LVDS CLOCK OUTPUT (DCO)3
Output Voltage High (DCO_P or DCO_N)
Output Voltage Low (DCO_P or DCO_N)
Output Differential Voltage, |VOD|
Output Offset Voltage, VOS
Output Impedance, Single-Ended, RO
RO Single-Ended Mismatch
Maximum Clock Rate
Min
825
175
−175
80
1250
825
175
−175
80
625
1025
150
1150
80
625
Typ
400
−400
1.2
400
−400
1.2
200
100
Max
1575
120
344
1575
120
1375
250
1250
120
10
Unit
mV
mV
mV
Ω
pF
MSPS
ps
mV
mV
mV
Ω
pF
MHz
mV
mV
mV
mV
Ω
%
MHz
1 DB0[x]P, DB0[x]N, DB1[x]P, and DB1[x]N pins.
2 DCI_P and DCI_N pins.
3 DCO_P and DCO_N pins with 100 Ω differential termination.
Rev.C | Page 5 of 64
5 Page 
Data Sheet
Pin No.
L1, M1
L2, M2
L3, M3
L4, M4
L5, M5
L6, M6
L7, M7
L8, M8
L9, M9
L10, M10
L11, M11
L12, M12
L13, M13
L14, M14
N1, P1
N2, P2
N3, P3
N4, P4
N5, P5
N6, P6
N7, P7
N8, P8
N9, P9
N10, P10
N11, P11
N12, P12
N13, P13
N14, P14
Mnemonic
NC, NC
NC, NC
NC, NC
DB1[0]P/DB1[0]N
DB1[1]P/DB1[1]N
DB1[2]P/DB1[2]N
DB1[3]P/DB1[3]N
DB1[4]P/DB1[4]N
DB1[5]P/DB1[5]N
DB1[6]P/DB1[6]N
DB1[7]P/DB1[7]N
DB1[8]P/DB1[8]N
DB1[9]P/DB1[9]N
DB1[10]P/DB1[10]N
NC, NC
NC, NC
NC, NC
DB0[0]P/DB0[0]N
DB0[1]P/DB0[1]N
DB0[2]P/DB0[2]N
DB0[3]P/DB0[3]N
DB0[4]P/DB0[4]N
DB0[5]P/DB0[5]N
DB0[6]P/DB0[6]N
DB0[7]P/DB0[7]N
DB0[8]P/DB0[8]N
DB0[9]P/DB0[9]N
DB0[10]P/DB0[10]N
AD9737A/AD9739A
Description
Do not connect to this pin.
Do not connect to this pin.
Do not connect to this pin.
Port 1 Positive/Negative Data Input Bit 0.
Port 1 Positive/Negative Data Input Bit 1.
Port 1 Positive/Negative Data Input Bit 2.
Port 1 Positive/Negative Data Input Bit 3.
Port 1 Positive/Negative Data Input Bit 4.
Port 1 Positive/Negative Data Input Bit 5.
Port 1 Positive/Negative Data Input Bit 6.
Port 1 Positive/Negative Data Input Bit 7.
Port 1 Positive/Negative Data Input Bit 8.
Port 1 Positive/Negative Data Input Bit 9.
Port 1 Positive/Negative Data Input Bit 10.
Do not connect to this pin.
Do not connect to this pin.
Do not connect to this pin.
Port 0 Positive/Negative Data Input Bit 0.
Port 0 Positive/Negative Data Input Bit 1.
Port 0 Positive/Negative Data Input Bit 2.
Port 0 Positive/Negative Data Input Bit 3.
Port 0 Positive/Negative Data Input Bit 4.
Port 0 Positive/Negative Data Input Bit 5.
Port 0 Positive/Negative Data Input Bit 6.
Port 0 Positive/Negative Data Input Bit 7.
Port 0 Positive/Negative Data Input Bit 8.
Port 0 Positive/Negative Data Input Bit 9.
Port 0 Positive/Negative Data Input Bit 10.
Rev. C | Page 11 of 64
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9739A.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD9739 | RF Digital-to-Analog Converter | Analog Devices |
| AD9739A | RF Digital-to-Analog Converters | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |