Datenblatt-pdf.com


AD8124 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD8124
Beschreibung Triple Differential Receiver
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
AD8124 Datasheet, Funktion
Data Sheet
Triple Differential Receiver with
200 Meter Adjustable Cable Equalization
AD8124
FEATURES
Compensates cables to 200 meters for wideband video
All resolutions through UXGA
Fast rise and fall times
8 ns with 2 V step at 200 meters of UTP cable
37 dB peak gain at 100 MHz
Two frequency response gain adjustment pins
High frequency peaking adjustment (VPEAK)
Broadband flat gain adjustment (VGAIN)
Pole location adjustment pin (VPOLE)
Compensates for variations between cables
Can be optimized for either UTP or coaxial cable
DC output offset adjust (VOFFSET)
Low output offset voltage: 24 mV
Compensates both RGB and YPbPr
Two on-chip comparators with hysteresis
Can be used for common-mode sync extraction
Available in 40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS
Keyboard-video-mouse (KVM)
Digital signage
RGB video over UTP cables
Professional video projection and distribution
HD video
Security video
GENERAL DESCRIPTION
The AD8124 is a triple, high speed, differential receiver and
equalizer that compensates for the transmission losses of UTP
and coaxial cables up to 200 meters in length. Various gain stages
are summed together to best approximate the inverse frequency
response of the cable. Logic circuitry inside the AD8124 controls
the gain functions of the individual stages so that the lowest
noise can be achieved at short-to-medium cable lengths. This
technique optimizes its performance for low noise, short-to-
medium range applications, while at the same time provides
the high gain bandwidth required for longer cable equalization
(up to 200 meters). Each channel features a high impedance
differential input that is ideal for interfacing directly with the cable.
FUNCTIONAL BLOCK DIAGRAM
VPEAK VPOLE VOFFSET VGAIN
AD8124
–INR
+INR
–ING
+ING
INB
+INB
–INCMP1
+INCMP1
–INCMP2
+INCMP2
Figure 1.
OUTR
OUTG
OUTB
OUTCMP1
OUTCMP2
The AD8124 has three control pins for optimal cable
compensation, as well as an output offset adjust pin. Two
voltage-controlled pins are used to compensate for different
cable lengths; the VPEAK pin controls the amount of high frequency
peaking and the VGAIN pin adjusts the broadband flat gain, which
compensates for the low frequency flat cable loss.
For added flexibility, an optional pole adjustment pin, VPOLE,
allows movement of the pole locations, allowing for the
compensation of different gauges and types of cable as well
as variations between different cables and/or equalizers. The
VOFFSET pin allows the dc voltage at the output to be adjusted,
adding flexibility for dc-coupled systems.
The AD8124 is available in a 6 mm × 6 mm, 40-lead LFCSP
and is rated to operate over the extended temperature range of
−40°C to +85°C.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD8124 Datasheet, Funktion
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage
Power Dissipation
Input Voltage (Any Input)
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
Rating
11 V
See Figure 2
VS− − 0.3 V to VS+ + 0.3 V
−65°C to +125°C
−40°C to +85°C
300°C
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions; that is, θJA is
specified for the device soldered in a circuit board in still air.
Table 3. Thermal Resistance with the Underside Pad
Connected to the Plane
Package Type/PCB Type
θJA Unit
40-Lead LFCSP/4-Layer
29 °C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8124 package
is limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8124. Exceeding a junction temperature
of 175°C for an extended time can result in changes in the
silicon devices, potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The power dissipation due to each load
current is calculated by multiplying the load current by the
AD8124
voltage difference between the associated power supply and the
output voltage. The total power dissipation due to load currents
is then obtained by taking the sum of the individual power
dissipations. RMS output voltages must be used when dealing
with ac signals.
Airflow reduces θJA. In addition, more metal directly in contact
with the package leads from metal traces, through holes, ground,
and power planes reduces the θJA. The exposed paddle on the
underside of the package must be soldered to a pad on the PCB
surface that is thermally connected to a solid plane (usually the
ground plane) to achieve the specified θJA.
Figure 2 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 40-lead LFCSP
(29°C/W) on a JEDEC standard 4-layer board with the underside
paddle soldered to a pad that is thermally connected to a PCB
plane. θJA values are approximations.
7
6
5
4
3
2
1
0
–40 –20
0
20 40 60 80
AMBIENT TEMPERATURE (°C)
Figure 2. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
Rev. A | Page 5 of 15

6 Page









AD8124 pdf, datenblatt
Data Sheet
APPLICATIONS INFORMATION
BASIC OPERATION
The AD8124 is easy to apply because it contains everything
on-chip needed for cable loss compensation. Figure 19 shows a
basic application circuit (power supplies not shown) with common-
mode sync pulse extraction that is compatible with the common-
mode sync pulse encoding technique used in the AD8134, AD8142,
AD8147, and AD8148 triple differential drivers. If sync extraction
is not required, the terminations can be single 100 Ω resistors,
and the comparator inputs can be left floating. In Figure 19, the
AD8124 feeds a high impedance input, such as a delay line or
crosspoint switch, and the additional gain of two that makes up
for double termination loss is not required.
COMPARATORS
In addition to general-purpose applications, the two on-chip
comparators can be used to extract video sync pulses from the
received common-mode voltages or to receive differential digital
information. Built-in hysteresis helps to eliminate false triggers
from noise. The Sync Pulse Extraction Using Comparators
section describes the sync extraction details.
AD8124
The comparator outputs have nearly 0 Ω output impedance and
are designed to drive source-terminated transmission lines. The
source termination technique uses a resistor in series with each
comparator output such that the sum of the comparator source
resistance (≈0 Ω) and the series resistor equals the transmission
line characteristic impedance. The load end of the transmission
line is high impedance. When the signal is launched into the source
termination, its initial value is one-half its source value because its
amplitude is divided by two in the voltage divider formed by the
source termination and the transmission line. At the load, the
signal experiences nearly 100% positive reflection due to the
high impedance load and is restored to nearly its full value. This
technique is commonly used in PCB layouts that involve high
speed digital logic.
Figure 18 shows how to apply the comparators with source
termination when driving a 50 Ω transmission line that is high
impedance at its receive end.
49.9
Z0 = 50
HIGH-Z
Figure 18. Using a Comparator with Source Termination
ANALOG
CONTROL
INPUTS
26
27
25
23
POWER-DOWN 28
CONTROL
VPEAK
VPOLE
VGAIN
VOFFSET
PD
RECEIVED
RED VIDEO
49.9
49.9
31
32
RECEIVED
GREEN VIDEO
49.9
49.9
34
35
RECEIVED
BLUE VIDEO
49.9
49.9
37
38
RED
GREEN
BLUE
AD8124
18 RED VIDEO OUT
15 GREEN VIDEO OUT
12 BLUE VIDEO OUT
1kBLUE CMV 2
1kRED CMV 3
GREEN
CMV
475
8
7
47pF
47pF
1
2
GND REFERENCE
24, 39
4 HSYNC OUT
6 VSYNC OUT
Figure 19. Basic Application Circuit with Common-Mode Sync Extraction
Rev. A | Page 11 of 15

12 Page





SeitenGesamt 16 Seiten
PDF Download[ AD8124 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
AD812Dual/ Current Feedback Low Power Op AmpAnalog Devices
Analog Devices
AD8120Triple Skew-Compensating Video Delay LineAnalog Devices
Analog Devices
AD8122Triple Differential ReceiverAnalog Devices
Analog Devices
AD8123Triple Differential ReceiverAnalog Devices
Analog Devices
AD8124Triple Differential ReceiverAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche