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P3P623S05B Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer P3P623S05B
Beschreibung Timing-Safe Peak EMI Reduction IC
Hersteller ON Semiconductor
Logo ON Semiconductor Logo 




Gesamt 11 Seiten
P3P623S05B Datasheet, Funktion
P3P623S05A/B and P3P623S09A/B
Timing-Safe™ Peak EMI
Reduction IC
General Features
Clock distribution with Timing-Safe™ Peak EMI
Reduction
Input frequency range: 20MHz - 50MHz
Multiple low skew Timing-safe™ Outputs:
P3P623S05: 5 Outputs
P3P623S09: 9 Outputs
Supply Voltage: 3.3V±0.3V
Packaging Information:
P3P623S05: 8 pin TSSOP
P3P623S09:16 pin TSSOP
True Drop-in Solution for Zero Delay Buffer
Functional Description
P3P623S05/09 is a versatile, 3.3V Zero-delay buffer
designed to distribute Timing-Safe™ clocks with Peak
EMI reduction. P3P623S05 is an eight-pin version,
accepts one reference input and drives out five low-skew
Timing-Safe™ clocks. P3P623S09 accepts one reference
input and drives out nine low-skew Timing-Safe™ clocks.
All parts have on-chip PLLs that lock to an input clock on
General Block Diagram
the CLKIN pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad, internal to the device.
Multiple P3P623S05 / P3P623S09 devices can accept
the same input clock and distribute it. In this case, the
skew between the outputs of the two devices is
guaranteed to be less than 700pS.
All outputs have less than 200pS of cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to
be less than ±350pS, and the output-to-output skew is
guaranteed to be less than 250pS.
Refer Spread Spectrum Control and Input-Output Skew
Table” for deviations and Input-Output Skew for
P3P623S05A/B and P3P623S09A/B devices.
P3P623S05/09 operates from a 3.3V supply and is
available in TSSOP package, as shown in the ordering
information table.
Application
P3P623S05/09 is targeted for use in Displays and
memory interface systems.
CLKIN
PLL
P3P623S05A/B
www.DataSheet4U.com
CLKOUT
CLK1
CLK2
CLK3
CLKIN
PLL
MUX
CLK4
S2
Select Input
Decoding
S1
P3P623S09A/B
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
©2010 SCILLC. All rights reserved.
July 2010 – Rev. 1
Publication Order Number:
P3P623S05/D






P3P623S05B Datasheet, Funktion
P3P623S05A/B and
P3P623S09A/B
Electrical Characteristics
Parameter
Description
Test Conditions
VIL Input LOW Voltage5
VIH Input HIGH Voltage5
IIL Input LOW Current
VIN = 0V
IIH Input HIGH Current
VOL Output LOW Voltage6
VOH Output HIGH Voltage6
VIN = VDD
IOL = 8mA
IOH = -8mA
IDD Supply Current
Unloaded outputs
Zo Output Impedance
Notes: 5. CLKIN input has a threshold voltage of VDD/2
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Min Typ
2.0
2.4
15
23
Switching Characteristics
Parameter
Test Conditions
Min
Input Frequency
20
Output Frequency
Duty Cycle 7,8 = (t2 / t1) * 100
Output Rise Time 7, 8
Output Fall Time 7, 8
Output-to-output skew 7, 8
30pF load
Measured at VDD/2
Measured between 0.8V and 2.0V
Measured between 2.0V and 0.8V
All outputs equally loaded
20
40
Delay, CLKIN Rising Edge to
CLKOUT Rising Edge 8
Measured at VDD /2
Device-to-Device Skew 8
Cycle-to-Cycle Jitter 7, 8
Measured at VDD/2 on the CLKOUT pins
of the device
Loaded outputs
PLL Lock Time 8
Stable power supply, valid clock presented
on CLKIN pin
Notes:
7. All parameters specified with 30pF loaded outputs.
8. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Typ
50
Max
0.8
50
100
0.4
Max
50
50
60
2.5
2.5
250
±350
700
±200
1.0
Unit
V
V
µA
µA
V
V
mA
Unit
MHz
MHz
%
nS
nS
pS
pS
pS
pS
mS
www.DataSheet4U.com
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