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PDF PCS1P2192A Data sheet ( Hoja de datos )
| Número de pieza | PCS1P2192A | |
| Descripción | VDP Multiple Pixel Clock Generator | |
| Fabricantes | PulseCore Semiconductor | |
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June 2009
rev 1.0
VDP Multiple Pixel Clock Generator
PCS1P2192A
Features
• Generates multiple clock outputs from 20MHz
external reference clock
• Input frequency: 20MHz
• Output frequencies:
• Selectable CLKOUT:
108MHz, 27MHz, 33.2MHz, 85MHz, 65MHz,
25MHz, 45MHz, and 40MHz
• REFOUT: 20MHz
• Operating Supply Voltage: 3.3V ± 0.3V
• Zero ppm frequency synthesis error on all clock
outputs
• Commercial temperature: 0°C to +85°C
• 8-pin SOIC package
Product Description
The PCS1P2192A is a clock generator that generates
multiple selectable pixel clock outputs for Video Display
Panel applications from an external 20MHz reference
clock. The PLL based clock generator is specifically
designed to provide zero ppm frequency synthesis error
on all clock outputs. Various pixel clock rates are
selectable through frequency selection pins S[2:0] (Refer
Frequency Selection Table) The device provides a
reference clock output additionally. Operating Supply
Voltage for this device is 3.3V± 0.3V. The device is
available in an 8 pin SOIC package, in commercial
temperature grade.
Applications
PCS1P2192A is targeted towards Video Display Panel
(VDP) applications like VGA, SVGA, XGA, WXGA,
UXGA.
Block Diagram
VDD [S2: S0]
CLKIN
www.DataSheet4U.com
PLL
GND
CLKOUT
REFOUT
PulseCore Semiconductor Corporation
2105 S. Bascom Ave Suite 210, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
1 page  
June 2009
rev 1.0
Typical Application Schematic
CLKIN 1 CLKIN
VDD
0Ω
0Ω VDD
0Ω
0Ω
2 GND
3 S0
4 S1
VDD 8
CLKOUT 7
REF 6
S2 5
Use either pull-up or pull-down
0Ω Resistor with [S2:S0] for selection of
CLKOUT frequencies
PCS1P2192A
VDD
0.01uF
GND
VDD
0Ω
0Ω
PCB Layout Recommendation
For optimum device performance, following guidelines are recommended.
• Dedicated VDD and GND planes.
• The device must be isolated from system power supply noise. A 0.01µF decoupling capacitor should be
mounted on the component side of the board as close to the VDD pin as possible. No vias should be
used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin and the ground via
should be kept as short as possible. All the VDD pins should have decoupling capacitors.
• In an optimum layout all components are on the same side of the board, minimizing vias through other
signal layers.
A typical layout is shown in the figure
As short
as possible
GND
VDD
www.DataSheet4U.com
VDP Multiple Pixel Clock Generator
Notice: The information in this document is subject to change without notice.
5 of 8
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet PCS1P2192A.PDF ] | |
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