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GS880F18T-14 Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS880F18T-14
Beschreibung 8Mb Sync Burst SRAMs
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 25 Seiten
GS880F18T-14 Datasheet, Funktion
100 Pin TQFP
Commercial Temp
Industrial Temp
Preliminary
GS880F18/36T-10/11/11.5/12/14
512K x 18, 256K x 36
8Mb Sync Burst SRAMs
www.D10atnaSshe-e1t44Un.csom
3.3V VDD
3.3V & 2.5V I/O
Features
• Flow through mode operation.
• 3.3V +10%/-5% Core power supply.
• 2.5V or 3.3V I/O supply.
• LBO pin for linear or interleaved burst mode.
• Internal input resistors on mode pins allow floating mode pins.
Default to Interleaved Pipelined Mode.
• Byte write (BW) and/or global write (GW) operation.
• Common data inputs and data outputs.
• Clock Control, registered, address, data, and control.
• Internal Self-Timed Write cycle.
• Automatic power-down for portable applications.
• 100-lead TQFP package
-10 -11 -11.5 -12 -14
Flow Through tKQ 10ns 11ns 11.5ns 12ns 14ns
2-1-1-1 tCycle 10ns 15ns 15ns 15ns 15ns
IDD 225mA 180mA 180mA 180mA 175mA
Functional Description
Applications
The GS880F18/32/36T is a 9,437,184 bit (8,388,608 bit for x32
version) high performance synchronous SRAM with a 2 bit burst
address counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPU’s, the device
now finds application in synchronous SRAM applications ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/O’s, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive edge triggered
clock input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Designing For Compatibility
The JEDEC Standard for Burst RAMS calls for a FT mode pin option
(pin 14 on TQFP). Board sites for Flow through Burst RAMS should
be designed with VSS connected to the FT pin location to ensure the
broadest access to multiple vendor sources. Boards designed with FT
pin pads tied low may be stuffed with GSI’s Pipeline/Flow through
configurable Burst RAMS or any vendor’s Flow through or
configurable Burst SRAM. Bumps designed with the FT pin location
tied High or floating must employ a non-configurable Flow through
Burst RAM, like this RAM, to achieve Flow through functionality.
88018/32/36TByte Write and Global Write
Byte write operation is performed by using byte write enable (BW)
input combined with one or more individual byte write signals (Bx). In
addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS880F18/32/36T operates on a 3.3V power supply and all
inputs/outputs are 3.3V and 2.5V compatible. Separate output power
(VDDQ) pins are used to de-couple output noise from the internal
circuit.
Rev: 1.03 3/2000
1/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N






GS880F18T-14 Datasheet, Funktion
GS880F18/32/36 Block Diagram
A0-An
Register
DQ
A0
A1
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
BB
BC
BD
D0 Q0
D1 Q1
Counter
Load
A0
A1
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
E1
E2
E3
0
G
Power Down
ZZ
Control
Note: Only x36 version shown for simplicity.
Register
DQ
Register
DQ
1
Preliminary
GS880F18/36T-10/11/11.5/12/14
www.DataSheet4U.com
A
Memory
Array
QD
36
4
36
DQx0-DQx9
Rev: 1.03 3/2000
6/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N

6 Page









GS880F18T-14 pdf, datenblatt
Preliminary
GS880F18/36T-10/11/11.5/12/14
Undershoot Measurement and Timing
VIH
VSS
50%
VSS-2.0V
20% tKC
www.DataSheet4U.com
Overshoot Measurement and Timing
VDD+-2.0V
50%
20% tKC
VDD
VIL
Note: This parameter is sample tested.
Package Thermal Characteristics
Rating
Layer Board Symbol
Max Unit Notes
Junction to Ambient (at 200 lfm)
single
RΘJA
40
°C/W
1,2
Junction to Ambient (at 200 lfm)
four
RΘJA
24
°C/W
1,2
Junction to Case (TOP)
RΘJC
9
°C/W
3
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87.
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
AC Test Conditions
Parameter
Input high level
Input low level
Input slew rate
Input reference level
Output reference level
Output load
Conditions
2.3V
0.2V
1V/ns
1.25V
1.25V
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ.
4. Device is deselected as defined by the Truth Table.
Rev: 1.03 3/2000
12/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N

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