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GS880F18AT-7.5 Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS880F18AT-7.5
Beschreibung 9Mb Synchronous Burst SRAMs
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 23 Seiten
GS880F18AT-7.5 Datasheet, Funktion
GS880F18/32/36AT-5.5/6/6.5/7/7.5/8.5
100-Pin TQFP
Commercial Temp
Industrial Temp
512K x 18, 256K x 32, 256K x 36
9Mb Synchronous Burst SRAMs
www.D5a.5taSnhsee8t4.5U.ncosm
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• Flow Through mode operation; Pin 14 = No Connect
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
Functional Description
Applications
The GS880F18/32/36AT is a 9,437,184-bit (8,388,608-bit for
x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Designing for Compatibility
The JEDEC standard for Burst RAMS calls for a FT mode pin
option on Pin 14. Board sites for flow through Burst RAMS
should be designed with VSS connected to the FT pin location
to ensure the broadest access to multiple vendor sources.
Boards designed with FT pin pads tied low may be stuffed with
GSI’s pipeline/flow through-configurable Burst RAMs or any
vendor’s flow through or configurable Burst SRAM. Boards
designed with the FT pin location tied high or floating must
employ a non-configurable flow through Burst RAM, like this
RAM, to achieve flow through functionality.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS880F18/32/36AT operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
Flow Through
2-1-1-1
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
-250 -225 -200 -166 -150 -133 Unit
5.5 6.0 6.5 7.0 7.5 8.5 ns
5.5 6.0 6.5 7.0 7.5 8.5 ns
175 165 160 150 145 135 mA
200 190 180 170 165 150 mA
Rev: 1.03 11/2004
1/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology






GS880F18AT-7.5 Datasheet, Funktion
A0An
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
BB
BC
BD
GS880F18/32/36AT-5.5/6/6.5/7/7.5/8.5
GS880F18/32/36A Block Diagram
www.DataSheet4U.com
Register
DQ
A0
A1
D0 Q0
D1 Q1
Counter
Load
A0
A1
Register
DQ
A
Memory
Array
QD
Register
DQ
Register
DQ
36
4
36
Register
DQ
Register
DQ
E1
E2
E3
NC
G
ZZ Power Down
Control
Note: Only x36 version shown for simplicity.
Register
DQ
Register
DQ
DCD=1
DQx1DQx9
Rev: 1.03 11/2004
6/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology

6 Page









GS880F18AT-7.5 pdf, datenblatt
GS880F18/32/36AT-5.5/6/6.5/7/7.5/8.5
Absolute Maximum Ratings
(All voltages reference to VSS)
www.DataSheet4U.com
Symbol
Description
Value
Unit
VDD Voltage on VDD Pins
0.5 to 4.6
V
VDDQ
Voltage in VDDQ Pins
0.5 to 4.6
V
VI/O
Voltage on I/O Pins
0.5 to VDDQ +0.5 (4.6 V max.)
V
VIN
Voltage on Other Input Pins
0.5 to VDD +0.5 (4.6 V max.)
V
IIN Input Current on Any Pin
+/20
mA
IOUT Output Current on Any I/O Pin
+/20
mA
PD Package Power Dissipation
1.5 W
TSTG Storage Temperature
55 to 125
oC
TBIAS
Temperature Under Bias
55 to 125
oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Power Supply Voltage Ranges
Parameter
Symbol Min. Typ. Max. Unit Notes
3.3 V Supply Voltage
VDD3
3.0
3.3
3.6
V
2.5 V Supply Voltage
VDD2
2.3
2.5
2.7
V
3.3 V VDDQ I/O Supply Voltage
VDDQ3
3.0
3.3
3.6
V
2.5 V VDDQ I/O Supply Voltage
VDDQ2
2.3
2.5
2.7
V
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be 2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Rev: 1.03 11/2004
12/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology

12 Page





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