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PDF ADP1850 Data sheet ( Hoja de datos )
| Número de pieza | ADP1850 | |
| Descripción | DC-to-DC Synchronous Buck Controller | |
| Fabricantes | Analog Integrations Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADP1850 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Wide Range Input, Dual/Two-Phase, DC-to-DC
Synchronous BucwkwCw.oDantatSrheoetl4lUe.crom
ADP1850
FEATURES
Wide range input: 2.75 V to 20 V
Power stage input voltage: 1 V to 20 V
Output voltage range: 0.6 V up to 90% VIN
Output current to more than 25 A per channel
Accurate current sharing between channels (interleaved)
Programmable frequency: 200 kHz to 1.5 MHz
180° phase shift between channels for reduced input
capacitance
±0.85% reference voltage accuracy from −40°C to +85°C
Integrated boost diodes
Power saving mode (PSM) at light loads
Accurate power good with internal pull-up resistor
Accurate voltage tracking capability
Independent channel precision enable
Overvoltage and overcurrent limit protection
Externally programmable soft start, slope compensation and
current sense gain
Synchronization input
Thermal overload protection
Input undervoltage lockout (UVLO)
Available in 32-lead 5 mm × 5 mm LFCSP
APPLICATIONS
High current single and dual output intermediate bus and
point of load converters requiring sequencing and
tracking capability, including converters for:
Point-of-load power supplies
Telecom base station and networking
Consumer
Industrial and instrumentation
Healthcare and medical
GENERAL DESCRIPTION
The ADP1850 is a configurable dual output or two-phase, single
output dc-to-dc synchronous buck controller capable of running
from commonly used 3.3 V to 12 V (up to 20 V) voltage inputs.
The device operates in current mode for improved transient
response and uses valley current sensing for enhanced noise
immunity.
The architecture enables accurate current sharing between
interleaved phases for high current outputs.
The ADP1850 is ideal in system applications requiring multiple
output voltages: the ADP1850 includes a synchronization fea-
ture to eliminate beat frequencies between switching devices;
provides accurate tracking capability between supplies and
includes precision enable for simple, robust sequencing.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
The ADP1850 provides high speed, high peak current drive
capability with dead-time optimization to enable energy
efficient power conversion. For low load operation, the device
can be configured to operate in power saving mode (PSM) by
skipping pulses and reducing switching losses to improve the
energy efficiency at light load and standby conditions.
The accurate current limit (±6%) allows the power architect to
design within a narrower range of tolerances and can reduce
overall converter size and cost.
The ADP1850 provides a configurable architecture capable
of wide range input operation to provide the designer with
maximum re-use opportunities and improved time to market.
Additional flexibility is provided by external programmability
of loop compensation, soft start, frequency setting, power
saving mode, current limit and current sense gain can all be
programmed using external components.
The ADP1850 includes a high level of integration in a small size
package. The start-up linear regulator and the boot-strap diode
for the high side drive are included. Protection features include:
undervoltage lock-out, overvoltage, overcurrent/short-circuit
and over temperature. The ADP1850 is available in a compact
32-lead LFCSP 5 mm × 5 mm thermally enhanced package.
TYPICAL OPERATION CIRCUIT
RRAMP1
VIN
RAMP1 VIN
ADP1850
EN1
EN2
VDL
VCCO
TRK1
TRK2
DH1
BST1
SW1
ILIM1
FB1
DL1
M1
L1
R11
M2
R12
VOUT1
PGOOD1
RCSG1
PGOOD2 PGND1
HI
LO
SYNC
FREQ
RRAMP2
RAMP2
VIN
COMP1
COMP2
SS1
SS2
AGND
DH2
BST2
SW2
ILIM2
FB2
DL2
PGND2
M3
L2
R21
RCSG2
M4
R22
VOUT2
Figure 1. Single Phase Circuit
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VIN, EN1/EN2, RAMP1/RAMP2
FB1/FB2, COMP1/COMP2, SS1/SS2, TRK1/TRK2,
FREQ, SYNC, VCCO, VDL, PGOOD1/PGOOD2
ILIM1/ILIM2, SW1/SW2 to PGND1/PGND2
BST1/BST2, DH1/DH2 to PGND1/PGND2
DL1/DL2 to PGND1/PGND2
BST1/BST2 to SW1/SW2
BST1/BST2 to PGND1/PGND2
20 ns Transients
SW1/SW2 to PGND1/PGND2
20 ns Transients
DL1/DL2, SW1/SW2, ILIM1/ILIM2 to
PGND1/PGND2
20 ns Negative Transients
PGND1/PGND2 to AGND
PGND1/PGND2 to AGND 20 ns Transients
θJA on Multilayer PCB (Natural Convection)1, 2
Operating Junction Temperature Range3
Storage Temperature Range
Maximum Soldering Lead Temperature
Rating
21 V
−0.3 V to +6 V
−0.3 V to +21 V
−0.3 V to +28 V
−0.3V to VCCO + 0.3 V
−0.3 V to +6 V
32 V
25 V
−8 V
−0.3 V to +0.3 V
−8 V to +4 V
32.6°C/W
−40°C to +125°C
−65°C to +150°C
260°C
1 Measured with exposed pad attached to PCB.
2 Junction-to-ambient thermal resistance (θJA) of the package was calculated
or simulated on multilayer PCB.
3 The junction temperature, TJ, of the device is dependent on the ambient
temperature, TA, the power dissipation of the device, PD, and the junction-to-
ambient thermal resistance of the package, θJA. Maximum junction
temperature is calculated from the ambient temperature and power
dissipation using the formula: TJ = TA + PD × θJA.
ADP1850
www.DataSheet4U.com
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to GND.
ESD CAUTION
Rev. 0 | Page 5 of 32
5 Page 
350
300
DH MINIMUM OFF TIME
250
200
150
DH MINIMUM ON TIME
100
50
2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0
VIN (V)
Figure 16. Typical DH Minimum On Time and Off Time
4
3
DH MINIMUM OFF TIME
2
1
DH MINIMUM ON TIME
0
–1
–2
–3
–4
–40 –15
10
35
60
85 110 135
TEMPERATURE (°C)
Figure 17. DH Minimum On Time and Off Time Over Temperature
35
VIN = 12V
34 OUTPUT IS LOADED
HS FET = BSC080N03LS
33 LS FET = BSC030N03LS
32
31
30
29
28
27
26 DEAD TIME BETWEEN SW FALLING EDGE
AND DL RISING EDGE, INCLUDING DIODE RECOVERY TIME
25
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
Figure 18. Dead Time vs. Temperature
ADP1850
45 TA =w25w°Cw.DataSheet4U.com
43 OUTPUT IS LOADED
HS FET = BSC080N03LS
41 LS FET = BSC030N03LS
39
37
35
33
31
29
27 DEAD TIME BETWEEN SW FALLING EDGE
AND DL RISING EDGE, INCLUDING DIODE RECOVERY TIME
25
0 5 10 15 20
VIN (V)
Figure 19. Dead Time vs. VIN
600
VIN = 2.75V TO 20V
580
560
540
520
500
480
460
440
420
400
–40 –15
10
35
60
85 110
TEMPERATURE (°C)
Figure 20. Gm of Error Amplifier vs. Temperature
135
4.5
4.0
VIN = 2.75V, SOURCING
3.5
3.0
VIN = 12V, SOURCING
2.5
2.0 VIN = 2.75V, SINKING
1.5
VIN = 12V, SINKING
1.0
0.5
0
–40 –15
10
35
60
85 110
TEMPERATURE (°C)
Figure 21. Driver Resistance vs. Temperature
135
Rev. 0 | Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADP1850.PDF ] | |
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