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C8051F99X Schematic ( PDF Datasheet ) - Silicon Laboratories

Teilenummer C8051F99X
Beschreibung (C8051F98X / C8051F99X) Capacitive Sensing MCU
Hersteller Silicon Laboratories
Logo Silicon Laboratories Logo 




Gesamt 30 Seiten
C8051F99X Datasheet, Funktion
C8051F99x-C8051F98x
Ultra Low Power, 8-2 kB Flash, Capacitive Sensing MCU
Ultra Low Power Consumption
- 150 µA/MHz in active mode (24.5 MHz clock)
- 2 µs wakeup time
- 10 nA sleep mode with memory retention
- 50 nA sleep mode with brownout detector
- 300 nA sleep mode with LFO
- 600 nA sleep mode with external crystal
Supply Voltage 1.8 to 3.6 V
- Built-in LDO regulator allows a high analog supply
voltage and low digital core voltage
- 2 built-in supply monitors (brownout detector) for
sleep mode and active modes
12-Bit or 10-Bit Analog to Digital Converter
- ±1 LSB INL (10-bit mode); ±1.5 LSB INL
(12-bit mode) no missing codes
- Programmable throughput up to 300 ksps
(10-bit mode) or 75 ksps (12-bit mode)
- Up to 10 external inputs
- On-chip voltage reference; 0.5x gain allows measur-
ing voltages up to twice the reference voltage
- 16-bit auto-averaging accumulator with burst mode
provides increased ADC resolution
- Data dependent windowed interrupt generator
- Built-in temperature sensor
Capacitive Sense Interface (F99x)
- Supports buttons, sliders, wheels, and capacitive
proximity sensing
- Fast 40 µs per channel conversion time
- 16-bit resolution, up to 14 input channels
- Auto scan and wake-on-touch
- Auto-accumulate up to 64x samples
Analog Comparator
- Programmable hysteresis and response time
- Configurable as wake-up or reset source
6-Bit Programmable Current Reference
- Up to ±500 µA, can be used as a bias or for
generating a custom reference voltage
- PWM enhanced resolution mode
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- 512 bytes RAM
- 8 kB (F990/1/6/7, F980/1/6/7), 4 kB (F982/3/8/9), or
2 kB (F985) Flash; in-system programmable
Digital Peripherals
- Up to 17 port I/O; high sink current and
programmable drive strength
Hardware SMBus™/I2C™, SPI™, and UART serial
ports available concurrently
- Four general purpose 16-bit counter/timers
- Programmable 16-bit counter/timer array with three
capture/compare modules and watchdog timer
Clock Sources
- Internal oscillators: 24.5 MHz, 2% accuracy
supports UART operation; 20 MHz low power
oscillator requires very little bias current.
- External oscillator: Crystal, RC, C, or CMOS Clock
- SmaRTClock oscillator: 32 kHz Crystal or internal
- Can switch between clock sources on-the-fly; useful
in implementing various power saving modes
On-Chip Debug
- On-chip debug circuitry facilitates full-speed, non-
intrusive in-system debug (no emulator required)
- Provides breakpoints, single stepping
- Inspect/modify memory and registers
- Complete development kit
Packages
- 20-pin QFN (3 x 3 mm)
- 24-pin QFN (4 x 4 mm)
- 24-pin QSOP (easy to hand-solder)
Temperature Range: –40 to +85 °C
ANALOG PERIPHERALS
DIGITAL I/O
A 12/10-bit
M 75/300 ksps IREF
U
X
ADC
TEMP
VREF
SENSOR VREG
Capacitive
Sense
+
VOLTAGE
COMPARATOR
UART
SMBus
SPI
PCA
Timer 0
Timer 1
Timer 2
Timer 3
CRC
Port 0
Port 1
Port 2
24.5 MHz PRECISION
INTERNAL OSCILLATOR
20 MHz LOW POWER
INTERNAL OSCILLATOR
External Oscillator
HARDWARE smaRTClock
HIGH-SPEED CONTROLLER CORE
8/4/2 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
CIRCUITRY
512B SRAM
POR WDT
Rev. 1.0 11/10
Copyright © 2010 by Silicon Laboratories
C8051F99x-C8051F98x
www.DataSheet.in






C8051F99X Datasheet, Funktion
C8051F99x-C8051F98x
22.3.SMBus Operation ........................................................................................... 235
22.3.1.Transmitter vs. Receiver ........................................................................ 235
22.3.2.Arbitration............................................................................................... 235
22.3.3.Clock Low Extension.............................................................................. 236
22.3.4.SCL Low Timeout................................................................................... 236
22.3.5.SCL High (SMBus Free) Timeout .......................................................... 236
22.4.Using the SMBus............................................................................................ 237
22.4.1.SMBus Configuration Register............................................................... 238
22.4.2.SMB0CN Control Register ..................................................................... 241
22.4.3.Hardware Slave Address Recognition ................................................... 244
22.4.4.Data Register ......................................................................................... 246
22.5.SMBus Transfer Modes.................................................................................. 247
22.5.1.Write Sequence (Master) ....................................................................... 247
22.5.2.Read Sequence (Master) ....................................................................... 248
22.5.3.Write Sequence (Slave) ......................................................................... 249
22.5.4.Read Sequence (Slave) ......................................................................... 250
22.6.SMBus Status Decoding................................................................................. 250
23. UART0.................................................................................................................... 255
23.1.Enhanced Baud Rate Generation................................................................... 256
23.2.Operational Modes ......................................................................................... 257
23.2.1.8-Bit UART ............................................................................................. 257
23.2.2.9-Bit UART ............................................................................................. 258
23.3.Multiprocessor Communications .................................................................... 258
24. Enhanced Serial Peripheral Interface (SPI0)...................................................... 263
24.1.Signal Descriptions......................................................................................... 264
24.1.1.Master Out, Slave In (MOSI).................................................................. 264
24.1.2.Master In, Slave Out (MISO).................................................................. 264
24.1.3.Serial Clock (SCK) ................................................................................. 264
24.1.4.Slave Select (NSS) ................................................................................ 264
24.2.SPI0 Master Mode Operation ......................................................................... 264
24.3.SPI0 Slave Mode Operation ........................................................................... 266
24.4.SPI0 Interrupt Sources ................................................................................... 267
24.5.Serial Clock Phase and Polarity ..................................................................... 267
24.6.SPI Special Function Registers ...................................................................... 269
25. Timers.................................................................................................................... 276
25.1.Timer 0 and Timer 1 ....................................................................................... 278
25.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 278
25.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 279
25.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 280
25.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 281
25.2.Timer 2 .......................................................................................................... 286
25.2.1.16-bit Timer with Auto-Reload................................................................ 286
25.2.2.8-bit Timers with Auto-Reload................................................................ 287
25.2.3.Comparator 0/SmaRTClock Capture Mode ........................................... 288
25.3.Timer 3 .......................................................................................................... 292
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C8051F99X pdf, datenblatt
C8051F99x-C8051F98x
Table 22.1. SMBus Clock Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 22.2. Minimum SDA Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . 239
Table 22.3. Sources for Hardware Changes to SMB0CN . . . . . . . . . . . . . . . . . . . 243
Table 22.4. Hardware Address Recognition Examples (EHACK = 1) . . . . . . . . . . 244
Table 22.5. SMBus Status Decoding With Hardware ACK Generation Disabled
(EHACK = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Table 22.6. SMBus Status Decoding With Hardware ACK Generation Enabled
(EHACK = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Table 23.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . 262
Table 23.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator . . . . . . . . . . . . . . . . . . . . . 262
Table 24.1. SPI Slave Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 25.1. Timer 0 Running Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 26.1. PCA Timebase Input Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Table 26.2. PCA0CPM and PCA0PWM Bit Settings for PCA
Capture/Compare Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Table 26.3. Watchdog Timer Timeout Intervals1 . . . . . . . . . . . . . . . . . . . . . . . . . . 310
12
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