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Teilenummer | R1EX24256BSAS0I |
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Beschreibung | Two-wire serial interface 256k EEPROM | |
Hersteller | Renesas Technology | |
Logo | ||
Gesamt 18 Seiten R1EX24256BSAS0I
R1EX24256BTAS0I
Two-wire serial interface
256k EEPROM (32-kword × 8-bit)
Datasheet
R10DS0007EJ0100
Rev.1.00
Aug. 04, 2010
Description
R1EX24xxx series are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). They
realize high speed, low power consumption and a high level of reliability by employing advanced MONOS memory
technology and CMOS process and low voltage circuitry technology. They also have a 64-byte page programming
function to make their write operation faster.
Features
• Single supply: 1.8 V to 5.5 V
• Two-wire serial interface (I2C serial bus)
• Clock frequency: 400 kHz
• Power dissipation:
Standby: 2 µA (max)
Active (Read): 1 mA (max)
Active (Write): 3 mA (max)
• Automatic page write: 64-byte/page
• Write cycle time: 5 ms
• Endurance: 1,000k Cycles @ 25°C
• Data retention: 100 Years @ 25°C
• Small size packages: SOP-8pin, TSSOP-8pin
• Shipping tape and reel
TSSOP 8-pin: 3,000 IC/reel
SOP 8-pin: 2,500 IC/reel
• Temperature range: −40 to +85°C
• Lead free products.
R10DS0007EJ0100 Rev.1.00
Aug. 04, 2010
www.DataSheet.in
Page 1 of 16
R1EX24256BSAS0I/R1EX24256BTAS0I
Pin Function
Serial Clock (SCL)
The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge clock data into
EEPROM device and negative edge clock data out of each device. Maximum clock rate is 400 kHz.
Serial Input/Output Data (SDA)
The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that pin is open-
drain driven structure. Use proper resistor value for your system by considering VOL, IOL and the SDA pin capacitance.
Except for a start condition and a stop condition which will be discussed later, the SDA transition needs to be completed
during the SCL low period.
Data Validity (SDA data change timing waveform)
SCL
SDA
Data
change
Data
change
Note: High-to-low and low-to-high change of SDA should be done during the SCL low period.
Device Address (A0, A1, A2)
Eight devices can be wired for one common data bus line as maximum. Device address pins are used to distinguish
each device and device address pins should be connected to VCC or VSS. When device address code provided from SDA
pin matches corresponding hard-wired device address pins A0 to A2, that one device can be activated.
Pin Connections for A0 to A2
Memory size Max connect number
A2
256k bit
8 VCC/VSS *1
Note: 1. During floating, "VCC/VSS" are fixed to VSS.
Pin connection
A1
VCC/VSS *1
A0
VCC/VSS *1
Note
Write Protect (WP)
When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in the following
table. Also, acknowledgment "0" is outputted after inputting device address and memory address. After inputting write
data, acknowledgment "1"(NO ACK) is outputted.
When the WP is low, write operation for all memory arrays are allowed. The read operation is always activated
irrespective of the WP pin status.
Write Protect Area
WP pin status
VIH
VIL
Write protect area
256k bit
Full (256k bit)
Normal read/write operation
R10DS0007EJ0100 Rev.1.00
Aug. 04, 2010
www.DataSheet.in
Page 6 of 16
6 Page R1EX24256BSAS0I/R1EX24256BTAS0I
Read Operation
There are three read operations: current address read, random read, and sequential read. Read operations are initiated
the same way as write operations with the exception of R/W = “1”.
Current Address Read:
The internal address counter maintains the last address accessed during the last read or write operation, with
incremented by one. Current address read accesses the address kept by the internal address counter. After receiving a
start condition and the device address word (R/W is “1”), the EEPROM outputs the 8-bit current address data from the
most significant bit following acknowledgment “0”. If the EEPROM receives acknowledgment “1” (no
acknowledgment) and a following stop condition, the EEPROM stops the read operation and is turned to a standby state.
In case the EEPROM has accessed the last address of the last page at previous read operation, the current address will
roll over and returns to zero address. In case the EEPROM has accessed the last address of the page at previous write
operation, the current address will roll over within page addressing and returns to the first address in the same page.
The current address is valid while power is on. The current address after power on will be indefinite. The random read
operation described below is necessary to define the memory address.
Current Address Read Operation
256k
Start
Device
address
1010
Read data (n+1)
R
ACK No ACK
R/W
Stop
R10DS0007EJ0100 Rev.1.00
Aug. 04, 2010
www.DataSheet.in
Page 12 of 16
12 Page | ||
Seiten | Gesamt 18 Seiten | |
PDF Download | [ R1EX24256BSAS0I Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
R1EX24256BSAS0A | Two-wire serial interface 256k EEPROM | Renesas Technology |
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