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PDF ADC08D1000QML Data sheet ( Hoja de datos )
| Número de pieza | ADC08D1000QML | |
| Descripción | 1 GSPS A/D Converter | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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ADC08D1000QML
November 9, 2009
High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D
Converter
General Description
The ADC08D1000 is a dual, low power, high performance
CMOS analog-to-digital converter that digitizes signals to 8
bits resolution at sampling rates up to 1.2 GSPS. Consuming
a typical 1.6 Watts at 1 GSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
full operating temperature range. The unique folding and in-
terpolating architecture, the fully differential comparator de-
sign, the innovative design of the internal sample-and-hold
amplifier and the self-calibration scheme enable a very flat
response of all dynamic parameters beyond Nyquist, produc-
ing a high 7.4 Effective Number Of Bits (ENOB) with a 498
MHz input signal and a 1 GHz sample rate while providing a
10-18 Bit Error Rate ( B.E.R.). Output formatting is offset binary
and the Low Voltage Differential Signaling (LVDS) digital out-
puts are compliant with IEEE 1596.3-1996, with the exception
of an adjustable common mode voltage between 0.8V and
1.13V.
Each converter has a 1:2 demultiplexer that feeds two LVDS
buses and reduces the output data rate on each bus to half
the sampling rate. The two converters can be interleaved and
used as a single 2 GSPS ADC.
The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced multi-layer ceramic quad package and operates
over the Military (-55°C ≤ TA ≤ +125°C) temperature range.
This part will work in a radiation environment, with ex-
cellent results, provided the guidelines in applications
section 2.1 are followed.
Features
■ Total Ionizing Dose
300 krad(Si)
■ Single Event Latch-Up
>120 MeV/mg/cm2
■ Internal Sample-and-Hold
■ Single +1.9V ±0.1V Operation
■ Choice of SDR or DDR output clocking
■ Interleave Mode for 2x Sampling Rate
■ Multiple ADC Synchronization Capability
■ Guaranteed No Missing Codes
■ Serial Interface for Extended Control
■ Fine Adjustment of Input Full-Scale Range and Offset
■ Duty Cycle Corrected Sample Clock
Key Specifications
■ Resolution
■ Max Conversion Rate
■ Bit Error Rate
■ ENOB @ 498 MHz Input
■ DNL
■ Power Consumption
— Operating
— Power Down Mode
8 Bits
1 GSPS (min)
10-18 (typ)
7.4 Bits (typ)
±0.15 LSB (typ)
1.6 W (typ)
3.5 mW (typ)
Applications
■ Communication Satellites/Systems
■ Direct RF Down Conversion
© 2009 National Semiconductor Corporation 201802
www.DataSheet.in
www.national.com
1 page  
Pin Functions
Pin No.
Symbol
18 CLK+
19 CLK-
Equivalent Circuit
Description
LVDS Clock input pins for the ADC. The differential clock signal
must be a.c. coupled to these pins. The input signal is sampled on
the falling edge of CLK+. See Section 1.1.2 for a description of
acquiring the input and Section 2.4 for an overview of the clock
inputs.
11 VINI+
10 VINI−
..
22 VINQ+
23 VINQ−
7 VCMO
31 VBG
126 CalRun
32 REXT
34 Tdiode_P
35 Tdiode_N
Analog signal inputs to the ADC. The differential full-scale input
range is 650 mVP-P when the FSR pin is low, or 870 mVP-P when
the FSR pin is high.
Common Mode Voltage. The voltage output at this pin is required
to be the common mode input voltage at VIN+ and VIN− when d.c.
coupling is used. This pin should be grounded when a.c. coupling
is used at the analog inputs. This pin is capable of sourcing or
sinking 100μA. See Section 2.3.
Bandgap output voltage capable of 100 μA source/sink.
Calibration Running indication. This pin is at a logic high when
calibration is running.
External bias resistor connection. Nominal value is 3.3k-Ohms
(±0.1%) to ground. See Section 1.1.1.
Temperature Diode Positive (Anode) and Negative (Cathode) for
die temperature measurements. See Section 2.7.2.
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5 Page 
AC Parameters
The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
870mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, VBG = Floating,
Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface
limits apply for TA = TMIN to TMAX (Note 5, Note 6)
Symbol Parameters
Conditions
Note Typical
s (Note 7)
Min
Max
Units
Sub -
groups
NORMAL MODE (Non DES) DYNAMIC CONVERTER CHARACTERISTICS
ENOB Effective Number of Bits
SINAD
Signal-to-Noise Plus
Distortion Ratio
SNR Signal-to-Noise Ratio
THD Total Harmonic Distortion
SFDR
fCLK1
Spurious Free Dynamic
Range
Maximum Input Clock
Frequency
fIN = 100 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
fIN = 100 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
fIN = 100 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
fIN = 100 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
Normal Mode (non DES)
7.5
7.4
7.4
47
46.3
46.3
48
47.1
47.1
-55
-55
-55
57
57
1.2
7.0
7.0
43.9
43.9
44
44
−47.5
−47.5
47
1.0
Bits
Bits
Bits
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
GHz
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
INTERLEAVE MODE (DES Pin 127=Float) - DYNAMIC CONVERTER CHARACTERISTICS
ENOB Effective Number of Bits
SINAD
Signal to Noise Plus
Distortion Ratio
SNR Signal to Noise Ratio
THD Total Harmonic Distortion
SFDR
Spurious Free Dynamic
Range
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
7.3
7.3
46
46
46.4
46.4
-58
-58
57
57
6.8
42.5
43
−49
47
Bits
Bits
dB
dB
dB
dB
dB
dB
dB
dB
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
AC Timing Parameters
The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
870mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, VBG = Floating,
Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface
limits apply for TA = TMIN to TMAX (Note 5, Note 6)
Symbol Parameters
Conditions
Notes
Typical
(Note 7)
Min
Max
Units
Sub -
groups
AC TIMING PARAMETERS
tRPW
Reset Pulse Width
4 Clock 9, 10, 11
Cycles
Serial Clock Low Time
4 ns 9, 10, 11
Serial Clock High Time
4 ns 9, 10, 11
tCAL_L CAL Pin Low Time
See Figure 9
640 Clock 9, 10, 11
Cycles
tCAL_H CAL Pin High Time
See Figure 9
640 Clock 9, 10, 11
Cycles
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| PDF Descargar | [ Datasheet ADC08D1000QML.PDF ] | |
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