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PDF 39VF1681 Data sheet ( Hoja de datos )
| Número de pieza | 39VF1681 | |
| Descripción | SST39VF1681 | |
| Fabricantes | Silicon Storage Technology | |
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DataSheet.in
16 Mbit (x8) Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
FEATURES:
SST39VF1681 / 16822.7V 16Mb (x8) MPF+ memories
Preliminary Specifications
• Organized as 2M x8
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Superior Reliability
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 9 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)
• Hardware Block-Protection/WP# Input Pin
– Top Block-Protection (top 64 KByte)
for SST39VF1682
– Bottom Block-Protection (bottom 64 KByte)
for SST39VF1681
• Sector-Erase Capability
– Uniform 4 KByte sectors
• Block-Erase Capability
– Uniform 64 KByte blocks
• Chip-Erase Capability
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin (RST#)
• Security-ID Feature
– SST: 128 bits; User: 128 bits
• Fast Read Access Time:
– 70 ns
– 90 ns
• Latched Address and Data
• Fast Erase and Byte-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Byte-Program Time: 7 µs (typical)
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bits
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and Command sets
• Packages Available
– 48-ball TFBGA (6mm x 8mm)
– 48-lead TSOP (12mm x 20mm)
PRODUCT DESCRIPTION
The SST39VF168x devices are 2M x8 CMOS Multi-Pur-
pose Flash Plus (MPF+) manufactured with SST’s propri-
etary, high performance CMOS SuperFlash technology.
The split-gate cell design and thick-oxide tunneling injec-
tor attain better reliability and manufacturability compared
with alternate approaches. The SST39VF168x write (Pro-
gram or Erase) with a 2.7-3.6V power supply. These
devices conform to JEDEC standard pinouts for x8 mem-
ories.
Featuring high performance Byte-Program, the
SST39VF168x devices provide a typical Byte-Program
time of 7 µsec. These devices use Toggle Bit or Data# Poll-
ing to indicate the completion of Program operation. To pro-
tect against inadvertent write, they have on-chip hardware
and Software Data Protection schemes. Designed, manu-
factured, and tested for a wide spectrum of applications,
these devices are offered with a guaranteed typical endur-
ance of 100,000 cycles. Data retention is rated at greater
than 100 years.
The SST39VF168x devices are suited for applications that
require convenient and economical updating of program,
configuration, or data memory. For all system applications,
©2003 Silicon Storage Technology, Inc.
S71243-03-000
11/03
1
they significantly improve performance and reliability, while
lowering power consumption. They inherently use less
energy during Erase and Program than alternative flash
technologies. The total energy consumed is a function of
the applied voltage, current, and time of application. Since
for any given voltage range, the SuperFlash technology
uses less current to program and has a shorter erase time,
the total energy consumed during any Erase or Program
operation is less than alternative flash technologies. These
devices also improve flexibility while lowering the cost for
program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
To meet high density, surface mount requirements, the
SST39VF168x are offered in both 48-ball TFBGA and
48-lead TSOP packages. See Figures 1 and 2 for pin
assignments.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
1 page  
DataSheet.in
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Product Identification
The Product Identification mode identifies the devices as
the SST39VF1681 and SST39VF1682, and manufacturer
as SST. Users may use the software Product Identifica-
tion operation to identify the part (i.e., using the device ID)
when using multiple manufacturers in the same socket.
For details, see Table 6 for software operation, Figure 11
for the software ID Entry and Read timing diagram, and
Figure 21 for the software ID Entry command sequence
flowchart.
TABLE 3: PRODUCT IDENTIFICATION
Manufacturer’s ID
Device ID
SST39VF1681
SST39VF1682
Address
0000H
0001H
0001H
Data
BFH
C8H
C9H
T3.1 1243
Product Identification Mode Exit/
CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
Preliminary Specifications
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the software ID Exit/CFI
Exit command is ignored during an internal Program or
Erase operation. See Table 6 for software command
codes, Figure 13 for timing waveform, and Figures 21 and
22 for flowcharts.
Security ID
The SST39VF168x devices offer a 256-bit Security ID
space which is divided into two 128-bit segments. The first
segment is programmed and locked at SST with a random
128-bit number. The user segment is left un-programmed
for the customer to program as desired.
To program the user segment of the Security ID, the user
must use the Security ID Byte-Program command. To
detect end-of-write for the SEC ID, read the toggle bits. Do
not use Data# Polling. Once this is complete, the Sec ID
should be locked using the User Sec ID Program Lock-Out.
This disables any future corruption of this space. Note that
regardless of whether or not the Sec ID is locked, neither
Sec ID segment can be erased.
The Security ID space can be queried by executing a
three-byte command sequence with Enter-Sec-ID com-
mand (88H) at address AAAH in the last byte sequence.
Execute the Exit-Sec-ID command to exit this mode. Refer
to Table 6 for more details.
FUNCTIONAL BLOCK DIAGRAM
X-Decoder
Memory Address
Address Buffer & Latches
CE#
OE#
WE#
WP#
RESET#
Control Logic
SuperFlash
Memory
Y-Decoder
I/O Buffers and Data Latches
DQ7 - DQ0
1243 B1.0
©2003 Silicon Storage Technology, Inc.
5
S71243-03-000
11/03
5 Page 
DataSheet.in
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Preliminary Specifications
TABLE 10: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V1
Limits
Symbol Parameter
IDD Power Supply Current
Read3
Program and Erase
ISB Standby VDD Current
IALP Auto Low Power
ILI Input Leakage Current
ILIW Input Leakage Current
on WP# pin and RST#
Min Max Units Test Conditions
Address input=VILT/VIHT2, at f=5 MHz,
VDD=VDD Max
18 mA CE#=VIL, OE#=WE#=VIH, all I/Os open
35 mA CE#=WE#=VIL, OE#=VIH
20 µA CE#=VIHC, VDD=VDD Max
20 µA CE#=VILC, VDD=VDD Max
All inputs=VSS or VDD, WE#=VIHC
1 µA VIN=GND to VDD, VDD=VDD Max
10 µA WP#=GND to VDD or RST#=GND to VDD
ILO Output Leakage Current
10 µA VOUT=GND to VDD, VDD=VDD Max
VIL Input Low Voltage
0.8 V VDD=VDD Min
VILC Input Low Voltage (CMOS)
0.3 V VDD=VDD Max
VIH Input High Voltage
0.7VDD
V VDD=VDD Max
VIHC
Input High Voltage (CMOS)
VDD-0.3
V VDD=VDD Max
VOL Output Low Voltage
0.2 V IOL=100 µA, VDD=VDD Min
VOH Output High Voltage
VDD-0.2
V IOH=-100 µA, VDD=VDD Min
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C
(room temperature), and VDD = 3V. Not 100% tested.
2. See Figure 17
3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V.
T10.8 1243
TABLE 11: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Units
TPU-READ1
Power-up to Read Operation
100 µs
TPU-WRITE1
Power-up to Program/Erase Operation
100 µs
T11.0 1243
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
Maximum
CI/O1
CIN1
I/O Pin Capacitance
Input Capacitance
VI/O = 0V
VIN = 0V
12 pF
6 pF
T12.0 1243
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Minimum Specification
Units
Test Method
NEND1,2
Endurance
10,000
Cycles
JEDEC Standard A117
TDR1
Data Retention
100
Years
JEDEC Standard A103
ILTH1
Latch Up
100 + IDD
mA JEDEC Standard 78
T13.2 1243
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a
higher minimum specification.
©2003 Silicon Storage Technology, Inc.
11
S71243-03-000
11/03
11 Page | ||
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