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PDF AD9963 Data sheet ( Hoja de datos )
| Número de pieza | AD9963 | |
| Descripción | (AD9961 / AD9963) Broadband MxFE | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
FEATURES
Dual 10-bit/12-bit, 100 MSPS ADC
SNR = 67 dB, fIN = 30.1 MHz
Dual 10-bit/12-bit, 170 MSPS DAC
ACLR = 74 dBc
5 channels of analog auxiliary input/output
Low power, <425 mW at maximum sample rates
Supports full and half-duplex data interfaces
Small 72-lead LFCSP lead-free package
APPLICATIONS
Wireless infrastructure
Picocell, femtocell basestations
Medical instrumentation
Ultrasound AFE
Portable instrumentation
Signal generators, signal analyzers
GENERAL DESCRIPTION
The AD9961/AD9963 are pin-compatible, 10-/12-bit, low
power MxFE® converters that provide two ADC channels with
sample rates of 100 MSPS and two DAC channels with sample
rates to 170 MSPS. These converters are optimized for transmit
and receive signal paths of communication systems requiring low
power and low cost. The digital interfaces provide flexible
clocking options. The transmit is configurable for 1×, 2×, 4×,
and 8× interpolation. The receive path has a bypassable 2×
decimating low-pass filter.
The AD9961 and AD9963 have five auxiliary analog channels.
Three are inputs to a 12-bit ADC. Two of these inputs can be
configured as outputs by enabling 10-bit DACs. The other
two channels are dedicated outputs from two independent
12-bit DACs.
The high level of integrated functionality, small size, and low
power dissipation of the AD9961/AD9963 make them well-
suited for portable and low power applications.
10-/12-Bit,
Low Power, Broadband MxFE
AD9961/AD9963
FUNCTIONAL BLOCK DIAGRAM
AD9961/AD9963
TEMPERATURE
SENSOR
DLLFILT
CLKP
CLKN
DLL AND
CLOCK
DISTRIBUTION
AUX
ADC
AUX
DAC
AUX
DAC
MUX
AUXIN1
AUXIO2
AUXIO3
TXCLK
TXIQ/TXnRX
TXD[11:0]
TRXCLK
TRXIQ
TRXD[11:0]
RESET
SDIO
SCLK
CS
INTERNAL
DATA
ASSEMBLER
LPF
1/2/4/8
LPF
1/2/4/8
LPF
1/2
LPF
1/2
SERIAL
PORT
LOGIC
REFERENCES
AND BIAS
12-BIT
DAC
12-BIT
DAC
12-BIT
ADC
12-BIT
ADC
AUX
DAC
AUX
DAC
LDO
VREGs
TXIP
TXIN
TXQP
TXQN
RXIP
RXIN
RXQP
RXQN
DAC12A
DAC12B
Figure 1.
PRODUCT HIGHLIGHTS
1. High Performance with Low Power Consumption.
The DACs operate on a single 1.8 V to 3.3 V supply.
Transmit path power consumption is <100 mW at
170 MSPS. Receive path power consumption is <350 mW
at 100 MSPS from 1.8 V supply. Sleep and power-down
modes are provided for low power idle periods.
2. High Integration.
The dual transmit and dual receive data converters, five
channels of auxiliary data conversion and clock generation
offer complete solutions for many modem designs.
3. Flexible Digital Interface.
The interface mates seamlessly to most digital baseband
processors.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.
1 page  
Data Sheet
AD9961/AD9963
TMIN to TMAX, RX33V = TXVDD = CLK33V = DRVDD = AUX33V = 3.3 V. All LDOs enabled, unless otherwise noted.
Table 3. Auxiliary Converter Specifications
AD9961
AD9963
Parameter
Min Typ Max Min Typ Max
AUXILIARY DAC12A/AUXDAC12B
Resolution
12 12
Differential Nonlinearity
±0.8 ±0.8
Gain Error
±2.0 ±2.0
Settling Time (±1%)
11
AUXILIARY DAC10A/DAC10B (Range = 0.5 V to 1.5 V)
Resolution
10 10
Differential Nonlinearity
±1.0 ±1.0
Gain Error
±2.0 ±2.0
Settling Time (±1%)
10 10
AUXILIARY ADC
Resolution
12 12
Differential Nonlinearity
−1.0 +1.0 −1.0 +1.0
Gain Error (Internal Reference)
−2.0 +2.0 −2.0 +2.0
Input Voltage Range
0 3.2 0 3.2
Maximum Sample Rate
50
50
Units
Bits
LSB
%
µs
Bits
LSB
%
µs
Bits
LSB
%
V
kHz
Rev. A | Page 5 of 60
5 Page 
Data Sheet
AD9961/AD9963
AUX33V 1
AUXADCREF 2
RXQP 3
RXQN 4
RXGND 5
RXBIAS 6
RX18V 7
RX33V 8
RX18VF 9
RXCML 10
RXGND 11
RXIN 12
RXIP 13
LDO_EN 14
RESET 15
SCLK 16
CS 17
SDIO 18
PIN 1
INDICATOR
AD9963
(TOP VIEW)
54 DLLFILT
53 DLL18V
52 DVDD18
51 DRVDD
50 TXD0
49 TXD1
48 TXD2
47 TXD3
46 TXD4
45 TXD5
44 TXD6
43 TXD7
42 TXD8
41 TXD9
40 TXD10
39 TXD11
38 TXIQ/TXnRX
37 TXCLK
NOTES
1. EXPOSED PAD MUST BE SOLDERED TO PCB.
Figure 3. AD9963 Pin Configuration
Table 9. AD9963 Pin Function Descriptions
Pin No. Mnemonic
Description
1 AUX33V
Analog Supply for the Auxiliary ADC and Auxiliary DACs (3.3 V ± 10%, 1.8 V ± 10% If Auxiliary ADC Is
Powered Down).
2
AUXADCREF
Reference Output (or input) for Auxiliary ADC.
3, 4 RXQP, RXQN Differential ADC Q Inputs. Full-scale input voltage range is 1.56 V p-p differential.
5, 11 RXGND
Receive Path Ground.
6 RXBIAS
External Bias Resistor Connection. This voltage is nominally 0.5 V. A 10 kΩ resistor can be connected
between this pin and analog ground to improve the Rx ADC full-scale accuracy.
7 RX18V
Output of RX18V Voltage Regulator.
8 RX33V
Input to RX18V and RX18VF Voltage Regulators (2.5 V to 3.3 V). If LDOs are not being used, short Pin 8 to
Pin 7.
9 RX18VF
Output of RX18VF Voltage Regulator.
10 RXCML
ADC Common-Mode Voltage Output.
12, 13
RXIN, RXIP
Differential ADC I Inputs. Full-scale input voltage range is 1.56 V p-p differential.
14 LDO_EN
Control pin for LDOs (GND = Disable all LDOs, Float = Enable DVDD18 LDO Only, DRVDD = Enable All
LDOs).
15 RESET
Reset. Active low to reset the configuration registers to default values and reset device.
16 SCLK
Clock Input for Serial Port.
17 CS
Active Low Chip Select.
18 SDIO
Bidirectional Data Line for Serial Port.
19, 34
DGND
Digital Core Ground.
20, 33, 51 DRVDD
Input/Output Pad Ring Supply Voltage (1.8 V to 3.3 V).
21 to 32 TRXD11 to TRXD0 ADC Output Data in Full Duplex Mode. ADC output data and DAC input data in half-duplex mode.
35 TRXIQ
Output Signal Indicating from Which ADC the Output Data Is Sourced.
36 TRXCLK
Qualifying Clock for the TRXD Bus.
37 TXCLK
Qualifying Clock for the TXD Bus. It can be configured as either an input or output.
38
TXIQ/TXnRX
Dual Function Pin. In half-duplex mode (TXnRX), this pin controls the direction of the TRX port. In full-
duplex mode (TXIQ), this input signal indicates to which DAC, I or Q, the TxDAC Input Data is intended.
39 to 50 TXD11 to TXD0
TxDAC Input Data.
52 DVDD18
Digital Core 1.8 V Supply.
53 DLL18V
Output of DLL18V Voltage Regulator.
Rev. A | Page 11 of 60
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9963.PDF ] | |
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