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Número de pieza | EDS2532EGBH-TT | |
Descripción | 256M bits SDRAM WTR | |
Fabricantes | Elpida Memory | |
Logotipo | ||
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No Preview Available ! PRELIMINARY DATA SHEET
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256M bits SDRAM
WTR (Wide Temperature Range)
EDS2532EGBH-TT (8M words × 32 bits)
Specifications
• Density: 256M bits
• Organization
2M words × 32 bits × 4 banks
• Package: 90-ball FBGA
Lead-free (RoHS compliant) and Halogen-free
• Power supply: VDD, VDDQ = 1.8V ± 0.1V
• Clock frequency: 166MHz/133MHz (max.)
• 2KB page size
Row address: A0 to A11
Column address: A0 to A8
• Four internal banks for concurrent operation
• Interface: LVCMOS
• Burst lengths (BL): 1, 2, 4, 8, full page
• Burst type (BT):
Sequential (1, 2, 4, 8, full page)
Interleave (1, 2, 4, 8)
• /CAS Latency (CL): 3
• Precharge: auto precharge option for each burst
access
• Driver strength: normal, 1/2, 1/4, 1/8
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 4096 cycles/64ms
Average refresh period: 15.6µs
• Operating ambient temperature range
TA = –20°C to +85°C
Features
• ×32 organization
• Single pulsed /RAS
• Burst read/write operation and burst read/single write
operation capability
• Byte control by DQM
• Wide temperature range
TA = −20°C to +85°C
Pin Configurations
/xxx indicates active low signal.
90-ball FBGA
123456789
A
DQ26 DQ24 VSS
B
DQ28 VDDQ VSSQ
C
VSSQ DQ27 DQ25
D
VSSQ DQ29 DQ30
E
VDDQ DQ31 NC
F
VSS DQM3 A3
G
A4 A5 A6
H
A7 A8 NC
J
CLK CKE A9
K
DQM1 NC NC
L
VDDQ DQ8 VSS
M
VSSQ DQ10 DQ9
N
VSSQ DQ12 DQ14
P
DQ11 VDDQ VSSQ
R
DQ13 DQ15 VSS
(Top view)
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
A10 A0 A1
NC BA1 A11
BA0 /CS /RAS
/CAS /WE DQM0
VDD DQ7 VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
A0 to A11
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQM0 to DQM3
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
DQ mask enable
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E1200E40 (Ver. 4.0)
Date Published December 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2007-2008
1 page EDS2532EGBH-TT
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DC Characteristics 1 (TA = –20°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)
Parameter
/CAS latency
Symbol Grade max.
Unit Test condition
Notes
Operating current
IDD1
-6D
-7B
Standby current in power down
IDD2P
Standby current in power down
(input signal stable)
IDD2PS
Standby current in non power down
IDD2N
Standby current in non power down
(input signal stable)
IDD2NS
Active standby current in power down
IDD3P
Active standby current in power down
(input signal stable)
IDD3PS
Active standby current in non power down IDD3N
Active standby current in non power down
(input signal stable)
IDD3NS
Burst operating current
IDD4
Refresh current
Self-refresh current
IDD5
IDD6
-6D
-7B
-6D
-7B
50
50
0.8
0.6
10
4.0
4.0
3.0
15
10
85
70
110
100
3.0
Burst length = 1
mA tRC = tRC (min.)
1, 2, 3
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
CKE ≤ 0.3V,
mA tCK = tCK (min.)
6
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
mA
CKE ≤ 0.3V, tCK = ∞
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
7
CKE, /CS = VIH,
mA tCK = tCK (min.)
4
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
mA
CKE = VIH, tCK = ∞,
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
8
CKE ≤ VIL,
mA tCK = tCK (min.)
1, 2, 6
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
mA
CKE ≤ VIL, tCK = ∞
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
2, 7
CKE, /CS = VIH,
mA tCK = tCK (min.)
1, 2, 4
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
mA
CKE = VIH, tCK = ∞,
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
2, 8
tCK = tCK (min.),
mA BL = 4
1, 2, 5
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
mA
tRC = tRC (min.)
VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
3
mA VIL ≤ 0.3V, VIH ≥ 0.8V × VDD
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Preliminary Data Sheet E1200E40 (Ver. 4.0)
5
5 Page DQ0 to DQ31 (input/output pins)
DQ pins have the same function as I/O pins on a conventional DRAM.
EDS2532EGBH-TT
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VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
Preliminary Data Sheet E1200E40 (Ver. 4.0)
11
11 Page |
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