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EDS2532EEBH-75TT Schematic ( PDF Datasheet ) - Elpida Memory

Teilenummer EDS2532EEBH-75TT
Beschreibung 256M bits SDRAM WTR
Hersteller Elpida Memory
Logo Elpida Memory Logo 




Gesamt 30 Seiten
EDS2532EEBH-75TT Datasheet, Funktion
DATA SHEET
www.DataSheet4U.com
256M bits SDRAM
WTR (Wide Temperature Range)
EDS2532EEBH-75TT (8M words × 32 bits)
Specifications
Density: 256M bits
Organization
2M words × 32 bits × 4 banks
Package: 90-ball FBGA
Lead-free (RoHS compliant)
Power supply: VDD, VDDQ = 1.8V ± 0.1V
Clock frequency: 133MHz (max.)
2KB page size
Row address: A0 to A11
Column address: A0 to A8
Four internal banks for concurrent operation
Interface: LVCMOS
Burst lengths (BL): 1, 2, 4, 8, full page
Burst type (BT):
Sequential (1, 2, 4, 8, full page)
Interleave (1, 2, 4, 8)
/CAS Latency (CL): 2, 3
Precharge: auto precharge operation for each burst
access
Driver strength: half/quarter
Refresh: auto-refresh, self-refresh
Refresh cycles: 4096 cycles/64ms
Average refresh period: 15.6µs
Operating ambient temperature range
TA = –20°C to +85°C
Features
• ×32 organization
Single pulsed /RAS
Burst read/write operation and burst read/single write
operation capability
Byte control by DQM
Wide temperature range
TA = –20°C to +85°C
Pin Configurations
/xxx indicates active low signal.
90-ball FBGA
123456789
A
DQ26 DQ24 VSS
B
DQ28 VDDQ VSSQ
C
VSSQ DQ27 DQ25
D
VSSQ DQ29 DQ30
E
VDDQ DQ31 NC
F
VSS DQM3 A3
G
A4 A5 A6
H
A7 A8 NC
J
CLK CKE A9
K
DQM1 NC NC
L
VDDQ DQ8 VSS
M
VSSQ DQ10 DQ9
N
VSSQ DQ12 DQ14
P
DQ11 VDDQ VSSQ
R
DQ13 DQ15 VSS
(Top view)
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
A10 A0 A1
NC BA1 A11
BA0 /CS /RAS
/CAS /WE DQM0
VDD DQ7 VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
A0 to A11
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQM0 to DQM3
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
DQ mask enable
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0910E10 (Ver. 1.0) This product became EOL in September, 2007.
Date Published May 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2006






EDS2532EEBH-75TT Datasheet, Funktion
EDS2532EEBH-75TT
www.DataSheet4U.com
DC Characteristics 2 (TA = –20°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)
Parameter
Symbol min.
max.
Unit Test condition
Notes
Input leakage current
ILI –1
Output leakage current
ILO –1.5
Output high voltage
VOH
VDD –0.2
Output low voltage
VOL
Note: 1. Driver strength is Half condition.
1
1.5
0.2
µA 0 VIN VDD
µA 0 VOUT VDD, DQ = disable
V IOH = –0.1 mA
1
V IOL = 0.1 mA
1
Pin Capacitance (TA = 25°C, VDD, VDDQ = 1.8V ± 0.1V)
Parameter
Symbol Pins
min. typ.
max.
Unit
Input capacitance
CI1 CLK
2.0 —
3.5 pF
Address, CKE, /CS,
CI2 /RAS, /CAS, /WE, 2.0
DQM
3.5 pF
Data input/output
capacitance
CI/O
DQ
3.0 —
5.5 pF
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1MHz, 0.5 × VDDQ, 200mV swing.
3. DQM = VIH to disable DOUT.
4. This parameter is sampled and not 100% tested.
Notes
1, 2, 4
1, 2, 4
1, 2, 3, 4
Data Sheet E0910E10 (Ver. 1.0)
6

6 Page









EDS2532EEBH-75TT pdf, datenblatt
EDS2532EEBH-75TT
www.DataSheet4U.com
Command Operation
Command Truth Table
The SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.
CKE
Function
Symbol n – 1 n
/CS /RAS /CAS /WE BA1 BA0 A10 A0 to A11
Device deselect
DESL
H
×
H× × × × × × ×
No operation
NOP H ×
L HHH× × × ×
Burst stop
BST H × L H H L × × × ×
Read
READ
H
×
L HL HVVL V
Read with auto precharge
READA H
×
L HL HVVHV
Write
WRIT
H
×
L HL L VVL V
Write with auto precharge
WRITA H
×
L HL L VVHV
Bank activate
ACT
H×
L L HHVVVV
Precharge select bank
PRE
H×
L L HL VVL ×
Precharge all banks
PALL
H
×
L L HL × × H×
Mode register set
MRS H ×
LLLLLLLV
Extended mode register set
EMRS H
×
L L L L HL L V
Remark: H: VIH. L: VIL. ×: VIH or VIL. V: Valid address input.
Device deselect command [DESL]
When this command is set (/CS is High), the SDRAM ignore command input at the clock. However, the internal
status is held.
No operation [NOP]
This command is not an execution command. However, the internal operations continue.
Burst stop command [BST]
This command can stop the current burst operation.
Column address strobe and read command [READ]
This command starts a read operation. In addition, the start address of burst read is determined by the column
address (see Address Pins Table in Pin Function) and the bank select address (BA0, BA1). After the read operation,
the output buffer becomes High-Z.
Read with auto-precharge [READA]
This command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4 or 8.
Column address strobe and write command [WRIT]
This command starts a write operation. When the burst write mode is selected, the column address (see Address
Pins Table in Pin Function) and the bank select address (BA0, BA1) become the burst write start address. When the
single write mode is selected, data is only written to the location specified by the column address (see Address Pins
Table in Pin Function) and the bank select address (BA0, BA1).
Write with auto-precharge [WRITA]
This command automatically performs a precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a
single write operation.
Data Sheet E0910E10 (Ver. 1.0)
12

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