PDF EDS2532CASG Data sheet ( Hoja de datos )

Número de pieza	EDS2532CASG
Descripción	256M bits SDRAM
Fabricantes	Elpida Memory
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DATA SHEET www.DataSheet4U.com 256M bits SDRAM EDS2532CASG (8M words × 32 bits) Specifications • Density: 256M bits • Organization ⎯ 2M words × 32 bits × 4 banks • Package: 90-ball FBGA ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 2.5V ± 0.2V • Clock frequency: 133MHz/100MHz (max.) • 2KB page size ⎯ Row address: A0 to A11 ⎯ Column address: A0 to A8 • Four internal banks for concurrent operation • Interface: LVTTL • Burst lengths (BL): 1, 2, 4, 8, full page • Burst type (BT): ⎯ Sequential (1, 2, 4, 8, full page) ⎯ Interleave (1, 2, 4, 8) • /CAS Latency (CL): 2, 3 • Precharge: auto precharge operation for each burst access • Refresh: auto-refresh, self-refresh • Refresh cycles: 4096 cycles/64ms ⎯ Average refresh period: 15.6μs • Operating ambient temperature range ⎯ TA = 0°C to +70°C Features • ×32 organization • Single pulsed /RAS • Burst read/write operation and burst read/single write operation capability • Byte control by DQM Pin Configurations /xxx indicates active low signal. 90-ball FBGA 1234567 A DQ13 VSS VDD B DQ11 DQ15 VSSQ C DQ14 DQ12 VDDQ D DQ10 DQ9 VSSQ E DQ8 VDD VDDQ F VSS DQM1 VDD G CLK CKE A9 H NC A8 A7 J A6 A5 A4 K A3 DQM3 VDD L VSS DQ31 VDDQ M DQ29 DQ30 VSSQ N DQ25 DQ27 VDDQ P DQ28 DQ24 VSSQ R DQ26 VSS VDD VSS VDD DQ2 VDDQ DQ0 DQ4 VSSQ DQ1 DQ3 VDDQ DQ5 DQ6 VSSQ DQ7 VDD VSS /WE DQM0 /CS /CAS /RAS NC A11 BA0 BA1 A10 A0 A1 A2 DQM2 VSSQ DQ16 VSS VDDQ DQ17 DQ18 VSSQ DQ22 DQ20 VDDQ DQ23 DQ19 VSS VDD DQ21 (Top view) A0 to A11 BA0, BA1 DQ0 to DQ31 /CS /RAS /CAS /WE DQM0 to DQM3 CKE CLK VDD VSS VDDQ VSSQ NC Address inputs Bank select address Data-input/output Chip select Row address strobe Column address strobe Write enable DQ mask enable Clock enable Clock input Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection Document No. E0541E21 (Ver. 2.1) Date Published February 2006 (K) Japan Printed in Japan URL: http://www.elpida.com This product became EOL in March, 2007. ©Elpida Memory, Inc. 2004-2006 1 page EDS2532CASG www.DataSheet4U.com DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) Parameter /CAS latency Symbol Grade max. Unit Test condition Notes Operating current IDD1 Standby current in power down IDD2P Standby current in power down (input signal stable) Standby current in non power down Standby current in non power down (input signal stable) Active standby current in power down Active standby current in power down (input signal stable) Active standby current in non power down Active standby current in non power down (input signal stable) IDD2PS IDD2N IDD2NS IDD3P IDD3PS IDD3N IDD3NS Burst operating current IDD4 Refresh current IDD5 Self refresh current IDD6 -75 -1A -75 -1A 125 3 2 20 9 4 3 50 30 155 125 265 255 3 mA Burst length = 1 tRC = tRC (min.) mA CKE = VIL, tCK = tCK (min.) 1, 2, 3 6 mA CKE = VIL, tCK = ∞ 7 mA CKE, /CS = VIH, tCK = tCK (min.) 4 mA CKE = VIH, tCK = ∞, /CS = VIH 8 mA CKE = VIL, tCK = tCK (min.) 1, 2, 6 mA CKE = VIL, tCK = ∞ 2, 7 mA CKE, /CS = VIH, tCK = tCK (min.) 1, 2, 4 mA CKE = VIH, tCK = ∞, /CS = VIH 2, 8 mA tCK = tCK (min.), BL = 4 1, 2, 5 mA tRC = tRC (min.) 3 mA VIH ≥ VDD – 0.2V VIL ≤ 0.2V Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CLK operating current. 7. After power down mode, no CLK operating current. 8. Input signals are VIH or VIL fixed. Data Sheet E0541E21 (Ver. 2.1) 5 5 Page EDS2532CASG www.DataSheet4U.com Command Operation Command Truth Table The SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins. CKE Function Symbol n – 1 n /CS /RAS /CAS /WE BA1,BA0 A10 Device deselect No operation DESL NOP H H × × H× × L HH ×× H× × × Burst stop BST H × L H H L × Read READ H × L HL HV Read with auto precharge READA H × L HL HV Write WRIT H × L HL L V Write with auto precharge WRITA H × L HL L V Bank activate ACT H × L L H H V Precharge select bank PRE H × L L H L V Precharge all banks PALL H × L L H L × × L H L H V L H Mode register set MRS H × L L L L L Remark: H: VIH. L: VIL. ×: VIH or VIL. V: Valid address input. L A0 to A11 × × × V V V V V × × V Device deselect command [DESL] When this command is set (/CS is High), the SDRAM ignore command input at the clock. However, the internal status is held. No operation [NOP] This command is not an execution command. However, the internal operations continue. Burst stop command [BST] This command can stop the current burst operation. Column address strobe and read command [READ] This command starts a read operation. In addition, the start address of burst read is determined by the column address (see Address Pins Table in Pin Function) and the bank select address (BA0, BA1). After the read operation, the output buffer becomes High-Z. Read with auto-precharge [READA] This command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4 or 8. Column address strobe and write command [WRIT] This command starts a write operation. When the burst write mode is selected, the column address (see Address Pins Table in Pin Function) and the bank select address (BA0, BA1) become the burst write start address. When the single write mode is selected, data is only written to the location specified by the column address (see Address Pins Table in Pin Function) and the bank select address (BA0, BA1). Write with auto-precharge [WRITA] This command automatically performs a precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a single write operation. Data Sheet E0541E21 (Ver. 2.1) 11 11 Page

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