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8632E Schematic ( PDF Datasheet ) - Maxim Integrated Products

Teilenummer 8632E
Beschreibung MAX8632E
Hersteller Maxim Integrated Products
Logo Maxim Integrated Products Logo 




Gesamt 29 Seiten
8632E Datasheet, Funktion
19-3623; Rev 0; 3/05
www.DataSheet4U.com
EVAALVUAAILTAIOBNLEKIT Integrated DDR Power-Supply Solution
for Desktops, Notebooks, and Graphic Cards
General Description
The MAX8632 integrates a synchronous-buck PWM con-
troller to generate VDDQ, a sourcing and sinking LDO lin-
ear regulator to generate VTT, and a 10mA reference
output buffer to generate VTTR. The buck controller drives
two external n-channel MOSFETs to generate output volt-
ages down to 0.7V from a 2V to 28V input with output cur-
rents up to 15A. The LDO can sink or source up to 1.5A
continuous and 3A peak current. Both the LDO output
and the 10mA reference buffer output can be made to
track the REFIN voltage. These features make the
MAX8632 ideally suited for DDR memory applications in
desktops, notebooks, and graphic cards.
The PWM controller in the MAX8632 utilizes Maxim’s
proprietary Quick-PWM™ architecture with programma-
ble switching frequencies of up to 600kHz. This control
scheme handles wide input/output voltage ratios with
ease and provides 100ns response to load transients
while maintaining high efficiency and a relatively con-
stant switching frequency. The MAX8632 offers fully pro-
grammable UVP/OVP and skip-mode options ideal in
portable applications. Skip mode allows for improved
efficiency at lighter loads.
The VTT and VTTR outputs track to within 1% of VREFIN / 2.
The high bandwidth of this LDO regulator allows excel-
lent transient response without the need for bulk capac-
itors, thus reducing cost and size.
The buck controller and LDO regulators are provided with
independent current limits. Adjustable lossless foldback
current limit for the buck regulator is achieved by monitor-
ing the drain-to-source voltage drop of the low-side
MOSFET. Additionally, overvoltage and undervoltage pro-
tection mechanisms are built in. Once the overcurrent
condition is removed, the regulator is allowed to enter
soft-start again. This helps minimize power dissipation
during a short-circuit condition. The MAX8632 allows flex-
ible sequencing and standby power management using
the SHDN and STBY inputs, which support all DDR
operating states.
The MAX8632 is available in a small 5mm × 5mm, 28-
pin thin QFN package.
Applications
DDR I and DDR II Memory Power Supplies
Desktop Computers
Notebooks and Desknotes
Graphic Cards
Game Consoles
RAID
Networking
Features
Buck Controller
Quick-PWM with 100ns Load-Step Response
Up to 95% Efficiency
2V to 28V Input Voltage Range
1.8V/2.5V Fixed or 0.7V to 5.5V Adjustable Output
Up to 600kHz Selectable Switching Frequency
Programmable Current Limit with Foldback
Capability
1.7ms Digital Soft-Start
Independent Shutdown and Standby Controls
Overvoltage-/Undervoltage-Protection Option
Power-Good Window Comparator
LDO Section
Fully Integrated VTT and VTTR Capability
VTT Has ±3A Sourcing/Sinking Capability
Only 20µF Ceramic Capacitance Required for VTT
VTT and VTTR Outputs Track VREFIN / 2
All-Ceramic Output-Capacitor Designs
1.0V to 2.8V Input Voltage Range
Power-Good Window Comparator
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX8632ETI+
-40°C to +85°C 28 Thin QFN 5mm × 5mm
+Denotes lead-free packaging.
Pin Configuration
TOP VIEW
VDD 22
PGND1 23
GND 24
SKIP 25
AVDD 26
SHDN 27
TPO 28
21 20 19 18 17 16 15
MAX8632
14 REFIN
13 VTTI
12 VTT
11 PGND2
10 VTTR
9 VTTS
8 SS
1 23 4 56 7
5mm x 5mm THIN QFN
Typical Operating Circuit appears at end of data sheet.
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.






8632E Datasheet, Funktion
www.DataSheet4U.com
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
Typical Operating Characteristics
(VVIN = 12V, VOUT = 2.5V, TON = GND, SKIP = AVDD, circuit of Figure 8, TA = +25°C, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT
(TON = GND)
100
90 fSW = 600kHz
80 VOUT = 2.5V
70
60 VOUT = 1.8V
50 VOUT = 1.5V
40
30
20
10
0
0.01
SKIP = GND
SKIP = AVDD
0.1 1 10
ILOAD (A)
100
SWITCHING FREQUENCY vs. INPUT VOLTAGE
(TON = GND)
700
680
660
640 ILOAD = 12A
620
600
580
560
540
520
500
480 ILOAD = 0A
460
440
420
400
4 6 8 10 12 14 16 18 20 22 24 26 28
VIN (V)
1.34
1.32
1.30
1.28
1.26
1.24
1.22
1.20
1.18
-3
VTT VOLTAGE
vs. VTT CURRENT
MAX8632 toc07
0.93
0.92
VVTT = 0.9V
0.91
0.90
0.89
0.88
VVTT = 1.25V
0.87
0.86
0.85
-2 -1 0 1 2 3
IVTT (A)
EFFICIENCY vs. LOAD CURRENT
(TON = OPEN)
100
90 fSW = 300kHz
80
70 VOUT = 2.5V
60 VOUT = 1.8V
50 VOUT = 1.5V
40
30
20
10
0
0.01
SKIP = GND
SKIP = AVDD
0.1 1
ILOAD (A)
10
100
SWITCHING FREQUENCY vs. TEMPERATURE
(TON = GND)
700
690
680
670
660 ILOAD = 12A
650
640
630
620
610
600
-40 -25 -10 5 20 35 50 65 80
TEMPERATURE (°C)
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.20
-15
VTTR VOLTAGE
vs. VTTR CURRENT
-10 -5 0 5
IVTTR (mA)
10
15
SWITCHING FREQUENCY vs. LOAD CURRENT
(TON = GND)
700
650
600
550
500
450
400
350
300
250
200
150 SKIP = GND
100
50 SKIP = AVDD
0
0 1 2 3 4 5 6 7 8 9 10 11 12
ILOAD (A)
OUTPUT VOLTAGE
vs. LOAD CURRENT
2.540
2.535
2.530
VIN = 15V,
TON = GND
2.525
2.520
2.515
2.510
2.505
2.500
SKIP = GND
SKIP = AVDD
2.495
2.490
0 2 4 6 8 10 12 14
ILOAD (A)
LINE REGULATION
(VOUT vs. VIN)
2.55
2.54
2.53
2.52 ILOAD = 0A
2.51
2.50
2.49 ILOAD = 12A
2.48
2.47
2.46
2.45
4 6 8 10 12 14 16 18 20 22 24 26 28
VIN (V)
6 _______________________________________________________________________________________

6 Page









8632E pdf, datenblatt
www.DataSheet4U.com
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
Detailed Description
The MAX8632 combines a synchronous-buck PWM con-
troller, an LDO linear regulator, and a 10mA reference out-
put buffer. The buck controller drives two external
n-channel MOSFETs to deliver load currents up to 12A
and generate voltages down to 0.7V from a +2V to +28V
input. The LDO linear regulator can sink and source up to
1.5A continuous and 3A peak current with relatively fast
response. These features make the MAX8632 ideally
suited for DDR memory applications.
The MAX8632 buck regulator is equipped with a fixed
switching frequency of up to 600kHz using Maxim’s
proprietary constant on-time Quick-PWM architecture.
This control scheme handles wide input/output voltage
ratios with ease, and provides 100ns “instant-on”
response to load transients, while maintaining high effi-
ciency with relatively constant switching frequency.
The buck controller, LDO, and a reference output
buffer are provided with independent current limits.
Lossless foldback current limit in the buck regulator is
achieved by monitoring the drain-to-source voltage
drop of the low-side FET. The ILIM input is used to
adjust this current limit. Overvoltage protection, if
selected, is achieved by latching the low-side synchro-
nous FET on and the high-side FET off when the output
voltage is over 116% of its set output. It also features
an optional undervoltage protection by latching the
MOSFET drivers to the OFF state during an overcurrent
condition, when the output voltage is lower than 70% of
the regulated output. This helps minimize power dissi-
pation during a short-circuit condition.
The current limit in the LDO and buffered reference out-
put buffer is ±5A and ±32mA, respectively, and neither
have the over- or undervoltage protection. When the
current limit in either output is reached, the output no
longer regulates the voltage, but regulates the current
to the value of the current limit.
+5V Bias Supply (VDD and AVDD)
The MAX8632 requires an external +5V bias supply in
addition to the input voltage (VIN). Keeping the bias sup-
ply external to the IC improves the efficiency and elimi-
nates the cost associated with the +5V linear regulator
that would otherwise be needed to supply the PWM cir-
cuit and the gate drivers. If stand-alone capability is
needed, then the +5V supply can be generated with an
external linear regulator such as the MAX1615. VDD,
AVDD, and IN can be connected together if the input
source is a fixed +4.5V to +5.5V supply.
VDD is the supply input for the buck regulator’s MOSFET
drivers, and AVDD supplies the power for the rest of
the IC. The current from the AVDD and VDD power
supply must supply the current for the IC and the gate
drive for the MOSFETs. This maximum current can be
estimated as:
( )IBIAS = IVDD + IAVDD + fSW × QG1 + QG2
where IVDD + IAVDD are the quiescent supply currents
into VDD and AVDD, QG1 and QG2 are the total gate
charges of MOSFETs Q1 and Q2 (at VGS = 5V) in the
Typical Applications Circuit of Figure 8, and fSW is the
switching frequency.
Free-Running Constant-On-Time PWM
The Quick-PWM control architecture is a pseudo-fixed-
frequency, constant on-time, current-mode regulator
with voltage feed-forward (Figure 1). This architecture
relies on the output filter capacitor’s ESR to act as a
current-sense resistor, so the output ripple voltage pro-
vides the PWM ramp signal. The control algorithm is
simple: the high-side switch on-time is determined
solely by a one-shot whose pulse width is inversely pro-
portional to input voltage and directly proportional to
the output voltage. Another one-shot sets a minimum
off-time of 300ns (typ). The on-time one-shot is trig-
gered if the error comparator is low, the low-side switch
current is below the valley current-limit threshold, and
the minimum off-time one-shot has timed out.
On-Time One-Shot (TON)
The heart of the PWM core is the one-shot that sets the
high-side switch on-time. This fast, low-jitter, adjustable
one-shot includes circuitry that varies the on-time in
response to input and output voltages. The high-side
switch on-time is inversely proportional to the input volt-
age (VIN) and is proportional to the output voltage:
( )tON
=
K×
VOUT
+
ILOAD × RDS(ON)Q2
VIN
where K (the switching period) is set by the TON input
connection (Table 1) and RDS(ON)Q2 is the on-resis-
tance of the synchronous rectifier (Q2) in the Typical
Applications Circuit (Figure 8). This algorithm results in
a nearly constant switching frequency despite the lack
of a fixed-frequency clock generator. The benefits of a
constant switching frequency are twofold:
1) The frequency can be selected to avoid noise-sensi-
tive regions such as the 455kHz IF band.
2) The inductor ripple-current operating point remains
relatively constant, resulting in an easy design
methodology and predictable output voltage ripple.
12 ______________________________________________________________________________________

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