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EN25Q80A Schematic ( PDF Datasheet ) - Eon Silicon Solution

Teilenummer EN25Q80A
Beschreibung 8 Megabit Serial Flash Memory
Hersteller Eon Silicon Solution
Logo Eon Silicon Solution Logo 




Gesamt 30 Seiten
EN25Q80A Datasheet, Funktion
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EN25Q80A
EN25Q80A
8 Megabit Serial Flash Memory with 4Kbyte Uniform Sector
FEATURES
Single power supply operation
- Full voltage range: 2.7-3.6 volt
Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
8 M-bit Serial Flash
- 8 M-bit/1024 K-byte/4096 pages
- 256 bytes per programmable page
Standard, Dual or Quad SPI
- Standard SPI: CLK, CS#, DI, DO, WP#
- Dual SPI: CLK, CS#, DQ0, DQ1, WP#
- Quad SPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3
High performance
- 100MHz clock rate for one data bit
- 80MHz clock rate for two data bits
- 80MHz clock rate for four data bits
Low power consumption
- 12 mA typical active current
- 1 μA typical power down current
Uniform Sector Architecture:
- 256 sectors of 4-Kbyte
- 16 blocks of 64-Kbyte
- Any sector or block can be erased individually
Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
High performance program/erase speed
- Page program time: 1.3ms typical
- Sector erase time: 90ms typical
- Block erase time 500ms typical
- Chip erase time: 8 seconds typical
Lockable 256 byte OTP security sector
Minimum 100K endurance cycle
Package Options
- 8 pins SOP 150mil body width
- 8 pins SOP 200mil body width
- 8 contact VDFN
- 8 pins PDIP
- All Pb-free packages are RoHS compliant
Industrial temperature Range
GENERAL DESCRIPTION
The EN25Q80A is an 8 Megabit (1024K-byte) Serial Flash memory, with advanced write protection
mechanisms. The EN25Q80A supports the standard Serial Peripheral Interface (SPI), and a high
performance Dual output as well as Quad I/O using SPI pins: Serial Clock, Chip Select, Serial DQ0(DI),
DQ1(DO), DQ2(WP#) and DQ3(NC). SPI clock frequencies of up to 80MHz are supported allowing
equivalent clock rates of 160MHz for Dual Output and 320MHz for Quad Output when using the
Dual/Quad Output Fast Read instructions. The memory can be programmed 1 to 256 bytes at a time,
using the Page Program instruction.
The EN25Q80A is designed to allow either single Sector/Block at a time or full chip erase operation. The
EN25Q80A can be configured to protect part of the memory as the software protected mode. The
device can sustain a minimum of 100K program/erase cycles on each sector or block.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
1
©2004 Eon Silicon Solution, Inc.,
Rev. D, Issue Date: 2009/10/13
www.eonssi.com






EN25Q80A Datasheet, Funktion
www.DataSheet4U.com
OPERATING FEATURES
EN25Q80A
Standard SPI Modes
The EN25Q80A is accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation
Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as
shown in Figure 3, concerns the normal state of the CLK signal when the SPI bus master is in standby
and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For
Mode 3 the CLK signal is normally high. In either case data input on the DI pin is sampled on the rising
edge of the CLK. Data output on the DO pin is clocked out on the falling edge of CLK.
Figure 3. SPI Modes
Dual SPI Instruction
The EN25Q80A supports Dual SPI operation when using the “ Dual Output Fast Read and Dual I/O
Fast Read “ (3Bh and BBh) instructions. These instructions allow data to be transferred to or from the
Serial Flash memory at two to three times the rate possible with the standard SPI. The Dual Read
instructions are ideal for quickly downloading code from Flash to RAM upon power-up (code-shadowing)
or for application that cache code-segments to RAM for execution. The Dual output feature simply
allows the SPI input pin to also serve as an output during this instruction. When using Dual SPI
instructions the DI and DO pins become bidirectional I/O pins; DQ0 and DQ1. All other operations use
the standard SPI interface with single output signal.
Quad SPI Instruction
The EN25Q80A supports Quad output operation when using the Quad I/O Fast Read (EBh).This
instruction allows data to be transferred to or from the Serial Flash memory at four to six times the rate
possible with the standard SPI. The Quad Read instruction offer a significant improvement in
continuous and random access transfer rates allowing fast code-shadowing to RAM or for application
that cache code-segments to RAM for execution. The EN25Q80A also supports full Quad Mode
function while using the Enable Quad I/O (EQIO) (38h). When using Quad SPI instruction the DI and
DO pins become bidirectional I/O pins; DQ0 and DQ1, and the WP# and NC pins become DQ2 and DQ3
respectively.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
6
©2004 Eon Silicon Solution, Inc.,
Rev. D, Issue Date: 2009/10/13
www.eonssi.com

6 Page









EN25Q80A pdf, datenblatt
Table 5. Manufacturer and Device Identification
OP Code
ABh
90h
9Fh
(M7-M0)
1Ch
1Ch
(ID15-ID0)
3014h
(ID7-ID0)
13h
13h
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EN25Q80A
Enable Quad I/O (EQIO) (38h)
The Enable Quad I/O (EQIO) instruction will enable the flash device for Quad SPI bus operation. Upon
completion of the instruction, all instructions thereafter will be 4-bit multiplexed input/output until a
power cycle or “ Reset Quad I/O instruction “ instruction, as shown in Figure 5. The device did not
support the Read Data Bytes (READ) (03h), Dual Output Fast Read (3Bh) and Dual Input/Output
FAST_READ (BBh) modes while the Enable Quad I/O (EQIO) (38h) turns on.
Figure 5. Enable Quad I/O Sequence Diagram
Reset Quad I/O (RSTQIO) (FFh)
The Reset Quad I/O instruction resets the device to 1-bit Standard SPI operation. To execute a Reset
Quad I/O operation, the host drives CS# low, sends the Reset Quad I/O command cycle (FFh) then,
drives CS# high. The device accepts either Standard SPI ( 8 clocks ) or Quad SPI ( 2 clocks) command
cycles. For Standard SPI, DQ [3:1] are don’t care for this command, but should be driven to VIH or VIL.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
12
©2004 Eon Silicon Solution, Inc.,
Rev. D, Issue Date: 2009/10/13
www.eonssi.com

12 Page





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