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PDF ADUC7124 Data sheet ( Hoja de datos )
| Número de pieza | ADUC7124 | |
| Descripción | ARM7TDMI MCU | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Precision Analog Microcontroller, 12-Bit Analog I/O, Large
Memory, ARM7TDMI MCU with Enhanced IRQ Handler
ADuC7124/ADuC7126
FEATURES
Analog input/output
Multichannel, 12-bit, 1 MSPS ADC
Up to 16 ADC channels
Fully differential and single-ended modes
0 V to VREF analog input range
12-bit voltage output DACs
4 DAC outputs available
On-chip voltage reference
On-chip temperature sensor (±3°C)
Voltage comparator
Microcontroller
ARM7TDMI core, 16-bit/32-bit RISC architecture
JTAG port supports code download and debug
Clocking options
Trimmed on-chip oscillator (±3%)
External watch crystal
External clock source up to 41.78 MHz
41.78 MHz PLL with programmable divider
Memory
126 kB Flash/EE memory, 32 kB SRAM
In-circuit download, JTAG-based debug
Software-triggered in-circuit reprogrammability
Vectored interrupt controller for FIQ and IRQ
8 priority levels for each interrupt type
Interrupt on edge or level external pin inputs
On-chip peripherals
2× fully I2C-compatible channels
SPI (20 MBPS in master mode, 10 MBPS in slave mode)
With 4-byte FIFO on input and output stages
2× UART channels
With 16-byte FIFO on input and output stages
Up to 40 GPIO port
All GPIOs are 5 V tolerant
4× general-purpose timers
Watchdog timer (WDT) and wake-up timer
Programmable logic array (PLA)
16 PLA elements
16-bit, 6-channel PWM
Power supply monitor
Power
Specified for 3 V operation
Active mode: 11.6 mA at 5 MHz, 33.3 mA at 41.78 MHz
Packages and temperature range
Fully specified for −40°C to +125°C operation
64-lead LFCSP (ADuC7124) and 80-lead LQFP (ADuC7126)
Tools
Low cost QuickStart development system
Full third-party support
APPLICATIONS
Industrial control and automation systems
Smart sensors, precision instrumentation
Base station systems, optical networking
Patient monitoring
FUNCTIONAL BLOCK DIAGRAM
ADC0
ADC15
CMP0
CMP1
CMPOUT
VREF
XCLKI
XCLKO
RST
MUX
OSC
AND PLL
PSM
POR
1MSPS
12-BIT ADC
TEMP
SENSOR
ADuC7124/ADuC7126
12-BIT
DAC
12-BIT
DAC
12-BIT
DAC
BAND GAP
REF
VECTORED
INTERRUPT
CONTROLLER
12-BIT
DAC
ARM7TDMI-BASED MCU WITH
ADDITIONAL PERIPHERALS
PLA
8k × 32 SRAM
63k × 16 FLASH/EEPROM
GPIO
4 GENERAL-
PURPOSE TIMERS
SPI, 2 × I2C,
2 × UART
JTAG
PWM
EXTERNAL
MEMORY
INTERFACE
DAC0
DAC1
DAC2
DAC3
Figure 1.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
GENERAL DESCRIPTION
The ADuC7124/ADuC7126 are fully integrated, 1 MSPS,
12-bit data acquisition system incorporating high performance
multichannel ADCs, 16-bit/32-bit MCUs, and Flash/EE memory
on a single chip.
The ADC consists of up to 12 single-ended inputs. An additional
four inputs are available but are multiplexed with the four DAC
output pins. The ADC can operate in single-ended or differen-
tial input mode. The ADC input voltage range is 0 V to VREF.
A low drift band gap reference, temperature sensor, and voltage
comparator complete the ADC peripheral set.
The DAC output range is programmable to one of three voltage
ranges. The DAC outputs have an enhanced feature of being
able to retain their output voltage during a watchdog or soft-
ware reset sequence.
The devices operate from an on-chip oscillator and a PLL
generating an internal high frequency clock of 41.78 MHz.
This clock is routed through a programmable clock divider
from which the MCU core clock operating frequency is
generated. The microcontroller core is an ARM7TDMI®,
16-bit/32-bit RISC machine, which offers up to 41 MIPS of
peak performance. Thirty-two kilobytes of SRAM and 126 kB
of nonvolatile Flash/EE memory are provided on-chip. The
ARM7TDMI core views all memory and registers as a single
linear array.
ADuC7124/ADuC7126
The ADuC7124/ADuC7126 contain an advanced interrupt
controller. The vectored interrupt controller (VIC) allows every
interrupt to be assigned a priority level. It also supports nested
interrupts to a maximum level of eight per IRQ and FIQ. When
IRQ and FIQ interrupt sources are combined, a total of 16
nested interrupt levels are supported.
On-chip factory firmware supports in-circuit download via the
UART serial interface port or the I2C port, while nonintrusive
emulation is also supported via the JTAG interface. These fea-
tures are incorporated into a low cost QuickStart™ development
system supporting this MicroConverter® family.
The parts contain a 16-bit PWM with six output signals.
For communication purposes, the parts contain 2× I2C channels
that can be individually configured for master or slave mode.
An SPI interface supporting both master and slave modes is
also provided. Thirdly, 2× UART channels are provided. Each
UART contains a configurable 16-byte FIFO with receive and
transmit buffers.
The parts operate from 2.7 V to 3.6 V and is specified over an
industrial temperature range of −40°C to +125°C. When operat-
ing at 41.78 MHz, the power dissipation is typically 120 mW.
The ADuC7124 is available in a 64-lead LFCSP package. The
ADuC7126 is available in a 80-lead LQFP package.
Rev. D | Page 5 of 110
5 Page 
Data Sheet
Table 5. SPI Master Mode Timing (Phase Mode = 0)
Parameter
Description
tSL SCLK low pulse width1
tSH SCLK high pulse width1
tDAV Data output valid after SCLK edge
tDOSU Data output setup before SCLK edge
tDSU Data input setup time before SCLK edge1
tDHD Data input hold time after SCLK edge1
tDF Data output fall time
tDR Data output rise time
tSR SCLK rise time
tSF SCLK fall time
Min
1 × tUCLK
2 × tUCLK
1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
MOSI
tSH
tSL
tDOSU
tDAV
tDF
MSB
tDR
BIT 6 TO BIT 1
ADuC7124/ADuC7126
Typ
(SPIDIV + 1) × tUCLK
(SPIDIV + 1) × tUCLK
Max
25
75
5 12.5
5 12.5
5 12.5
5 12.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSR tSF
LSB
MISO
MSB IN
BIT 6 TO BIT 1
LSB IN
tDSU
tDHD
Figure 4. SPI Master Mode Timing (Phase Mode = 0)
Rev. D | Page 11 of 110
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADUC7124.PDF ] | |
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