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PDF AD5735 Data sheet ( Hoja de datos )
| Número de pieza | AD5735 | |
| Descripción | Quad Channel 16-Bit Serial Input - 4-20mA & Voltage Output DAC Dynamic Power Control | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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1. AD5735  Hay una vista previa y un enlace de descarga de AD5735 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Preliminary Technical Data
FEATURES
16/12-Bit Resolution and Monotonicity
Dynamic Power Control for Thermal Management
Voltage or Current Output on the Same Pin
IOUT Range: 0mA-20mA, 4mA–20mA or 0mA–24mA
±0.05% Total Unadjusted Error (TUE) Max
VOUT Range: 0-5V, 0-10V, ±5V, ±10V,±6V,±12V
±0.04% Total Unadjusted Error (TUE) Max
User programmable Offset and Gain
On Chip Diagnostics
On-Chip Reference (±5 ppm/°C)
−40°C to +105°C Temperature Range
APPLICATIONS
Process Control
Actuator Control
PLC’s
PRODUCT HIGHLIGHTS
Dynamic Power Control for Thermal management
16bit performance
Multi-channel
Quad Cwhwwa.DnantaeShle,et41U6.co-mBit,
Serial Input, 4-20mA & Voltage Output DAC,
Dynamic Power Control
AD5755/AD5735
GENERAL DESCRIPTION
The AD5755/AD5735 is a quad, voltage and current output
DAC, which operates with a power supply range from -26v to
+33v. On chip dynamic power control minimizes package
power dissipation in current mode. This is achieved by
regulating the voltage on the output driver from between 7V-
30V.
The part uses a versatile 3-wire serial interface that operates at
clock rates up to 30 MHz and that is compatible with standard
SPI®, QSPI™, MICROWIRE™, DSP and microcontroller
interface standards. The interface also features optional CRC-8
packet error checking as well as a watchdog timer that monitors
activity on the interface.
Table 1. Complementary Devices
Part No.
Description
ADR445
5V, Ultralow Noise, LDO XFET Voltage
Reference with Current Sink and Source
ADP1871
Synchronous Buck Controller with Constant
On-Time, Valley Current Mode, and Power
Save Mode
Figure 1.
Rev. PrG
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
AD5755/AD5735www.DataSheet4U.com
Parameter1
Gain TC2
Full-Scale Error
Full-Scale TC2
OUTPUT CHARACTERISTICS2
Current Loop Compliance Voltage
Min
−TBD
−0.12
−TBD
−TBD
Output Current Drift vs. Time
Resistive Load
Inductive Load
DC PSRR
Output Impedance
REFERENCE INPUT/OUTPUT
Reference Input2
Reference Input Voltage
DC Input Impedance
Reference Output
Output Voltage
Reference TC2,3
Output Noise (0.1 Hz to 10 Hz)2
Noise Spectral Density2
Output Voltage Drift vs. Time2
4.95
5
4.998
-10
Capacitive Load2
Load Current
Short Circuit Current
Line Regulation2
Load Regulation2
Thermal Hysteresis2
DC-DC
SWITCH
SWITCH On Resistance
SWITCH Leakage Current
Peak Current Limit
OSCILLATOR
Oscillator Frequency
Maximum Duty Cycle
DIGITAL INPUTS2
VIH, Input High Voltage
VIL, Input Low Voltage
TBD
2
Typ Max
+TBD
+0.12
TBD +TBD
+TBD
Unit
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
Test Conditions/Comments
TA = 25°C
TBD AVDD - V max
2.5
±TB ppm FSR
D
±TB ppm FSR
D
See Ω max
Com
men
t
See H max
Com
men
t
TBD µA/V
TBD µA/V
50 MΩ
Drift after 500 hours, TJ = 150°C
(this is included in the TUE specifications)
Drift after 1000 hours, TJ = 150°C
(this is included in the TUE specifications)
Chosen such that compliance is not exceeded. Plus
see graph on load vs. AVcc and DCDC switching freq.
Will need appropriate cap at higher inductance values.
See Page X of Datasheet.
5 5.05
TBD
5 5.002
±5 10
TBD
TBD
±TB
D
±TB
D
TBD
5
7
10
TBD
TBD
V nom
MΩ min
For specified performance
V
ppm/°C
µV p-p typ
nV/√Hz typ
ppm
ppm
nF
mA
mA
ppm/V
ppm/mA
ppm
TA = 25°C
At 10 kHz
Drift after 500 hours, TJ = 150°C
Drift after 1000 hours, TJ = 150°C
0.5 ohm
TBD uA
0.8 A
TBD TBD
TBD
KHz
%
V
0.8 V
Rev. PrG | Page 5 of 34
VIN=TBD, IOUT=TBD, RLOAD=TBD
JEDEC compliant
5 Page 
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Table 5.
Parameter
AVDD to AGND, DGND
AVSS to AGND, DGND
AVDD to AVSS
AVcc to AGND
DVDD to DGND
Digital Inputs to DGND
Digital Outputs to DGND
REFIN/REFOUT to AGND
VOUT A,B,C,D to AGND
−VSENSEA,B,C,D / +VSENSEA,B,C,D to AGND
COMPLVA,B,C,D to AGND
IOUT A,B,C,D to AGND
RSETA,B,C,D to AGND
SWA,B,C,D / VBOOSTA,B,C,D to AGND
COMPDCDC_A,B,C,D to AGND
AGND, GNDSWA,B,C,D to DGND
Operating Temperature Range (TA)
Industrial1
Storage Temperature Range
Junction Temperature (TJ max)
64-Lead LFCSP
θJA Thermal Impedance2
Power Dissipation
Lead Temperature
Soldering
Rating
−0.3 V to +33 V
+0.3 V to −28 V
−0.3 V to +60 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to DVDD + 0.3 V or
+7 V (whichever is less)
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V or +7
V (whichever is less)
AVSS to VBOOST or 33V if using
the DC-DC circuitry.
AVSS to VBOOST or 33V if using
the DC-DC circuitry.
0.3 V to +5 V
AVSS to VBOOST or 33V if using
the DC-DC circuitry.
−0.3 V to AVDD + 0.3 V or +7
V (whichever is less)
−0.3 to +33 V
−0.3 V to +5 V
−0.3 V to +0.3 V
−40°C to +105°C
−65°C to +150°C
125°C
20°C/W
(TJ max – TA)/θJA
JEDEC Industry Standard
J-STD-020
1 Power dissipated on chip must be derated to keep the junction temperature
below 125°C
2 Based on a JEDEC 4 layer test board
AD5755/AD5735www.DataSheet4U.com
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. PrG | Page 11 of 34
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD5735.PDF ] | |
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