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AD5737 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5737
Beschreibung Quad Channel 16-Bit Serial Input - 4-20mA Output DAC Dynamic Power Control : HART Connectivity
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 31 Seiten
AD5737 Datasheet, Funktion
Preliminary Technical Data
FEATURES
16/12-Bit Resolution and Monotonicity
Dynamic Power Control for Thermal Management
IOUT Range: 0mA-20mA, 4mA–20mA or 0mA–24mA
±0.05% Total Unadjusted Error (TUE) Max
User programmable Offset and Gain
On Chip Diagnostics
On-Chip Reference (±5 ppm/°C Max)
−40°C to +105°C Temperature Range
APPLICATIONS
Process Control
Actuator Control
PLC’s
HART Network Connectivity
PRODUCT HIGHLIGHTS
Dynamic Power Control for Thermal management
16bit performance
Multi-channel
HART Compliant
Quad Cwhwwa.DnantaeShle,et41U6.co-mBit,
Serial Input, 4-20mA Output DAC,
Dynamic Power Control, HART Connectivity
AD5757/AD5737
GENERAL DESCRIPTION
The AD5757/AD5737 is a quad, current output DAC, which
operates with a power supply of up to +33v. On chip dynamic
power control minimizes package power dissipation in current
mode. This is achieved by regulating the voltage on the output
driver from between 7V-30V.
Each channel has a corresponding CHART pin so that HART
signals can be coupled onto the AD5757/AD5737’s current
output.
The part uses a versatile 3-wire serial interface that operates at
clock rates up to 30 MHz and that is compatible with standard
SPI®, QSPI™, MICROWIRE™, DSP and microcontroller
interface standards. The interface also features optional CRC-8
packet error checking as well as a watchdog timer that monitors
activity on the interface.
Table 1. Complementary Devices
Part No.
Description
ADR445
5V, Ultralow Noise, LDO XFET Voltage
Reference with Current Sink and Source
ADP1871
Synchronous Buck Controller with Constant
On-Time, Valley Current Mode, and Power
Save Mode
Figure 1.
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.






AD5737 Datasheet, Funktion
AD5757/AD5737
Preliminary Technical Datawww.DataSheet4U.com
TIMING CHARACTERISTICS
AVDD = 15V, AVSS = 0V/-15 V, VBOOSTA,B,C,D = +10.8 V to +33 V, DVDD = AVCC = 2.7 V to 5.5 V, DCDC disabled, AGND = DGND =
GNDSWA,B,C,D = 0 V, REFIN= +5, VOUT : RL = 1kΩ, CL = 220pF, IOUT : RL = 300, all specifications TMIN to TMAX unless otherwise noted.
Table 4.
Parameter1, 2, 3
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
Limit at TMIN, TMAX
33
13
13
13
13
198
5
5
20
5
10
500
See AC Performance
Characteristics
10
TBD
25
20
5
500
700
20
5
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs min
µs min
ns min
ns max
µs max
ns min
µs max
ns max
µs min
µs min
ns min
ns min
µs min
µs min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24/32nd SCLK falling edge to SYNC rising edge
SYNC high time
Data setup time
Data hold time
SYNC rising edge to LDAC falling edge (all DACs updated or any
channel has digital slew rate control enabled)
SYNC rising edge to LDAC falling edge (single DAC updated)
LDAC pulse width low
LDAC falling edge to DAC output response time
DAC output settling time
CLEAR high time
CLEAR activation time
SCLK rising edge to SDO valid (CL SDO = 35 pF)
SYNC rising edge to DAC output response time (LDAC = 0) (all DACs
updated)
SYNC rising edge to DAC output response time (LDAC = 0) (single
DAC updated)
LDAC falling edge to SYNC rising edge
RESET pulsewidth
SYNC high to next SYNC low (Ramp enabled)
SYNC high to next SYNC low (Ramp disabled)
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.
3 See Figure 2 , Figure 3 , Figure 4 and Figure 5
Rev. PrD | Page 6 of 31

6 Page









AD5737 pdf, datenblatt
AD5757/AD5737
Preliminary Technical Datawww.DataSheet4U.com
Pin No.
53
54
55
56
Mnemonic
AVSS
IOUT_D
N/C
VBOOST_D
57 COMPDCDC_D
58 IGATED
59 CHARTD
60 N/C
61 REFIN
62 REFOUT
63 RSET_D
64 RSET_C
Exposed PADDLE
Description
Negative Analog Supply Pin.
Current Output Pin for DAC Channel D.
No Connection. Do not connect to this pin.
Supply for channel D’s current output stage (See Figure 14). To use the DC-DC feature of the device,
connect as shown in Figure 1.
DC-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the
feedback loop of channel D’s DC-DC converter.
Optional connection for external pass transistor. Not required when using DC-DC. Should be left unconnected.
Hart Input Connection for DAC Channel D
No Connection. Do not connect to this pin.
External Reference Voltage Input.
Internal Reference Voltage Output.
An external, precision, low drift 15 k Ω current setting resistor can be connected to this pin to improve the
IOUT_D temperature drift performance. See the Features section.
An external, precision, low drift 15 k Ω current setting resistor can be connected to this pin to improve the
IOUT_C temperature drift performance. See the Features section.
CONNECTED TO AVss SUPPLY
Rev. PrD | Page 12 of 31

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