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AGL125 Schematic ( PDF Datasheet ) - Actel Corporation

Teilenummer AGL125
Beschreibung (AGLxxx) IGLOO Low-Power Flash FPGAs
Hersteller Actel Corporation
Logo Actel Corporation Logo 




Gesamt 30 Seiten
AGL125 Datasheet, Funktion
IGLOO Low-Power Flash FPGAs
with Flash*Freeze Technology
www.DataSheet4U.com
v1.3
®
Features and Benefits
Low Power
• 1.2 V to 1.5 V Core Voltage Support for Low Power
• Supports Single-Voltage System Operation
• 5 µW Power Consumption in Flash*Freeze Mode
• Low-Power Active FPGA Operation
• Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
• Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze
Mode
High Capacity
• 15 k to 1 Million System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal, Flash-Based CMOS Process
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design When Powered Off
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption (except ARM®-enabled IGLOO®
devices) via JTAG (IEEE 1532–compliant)1
• FlashLock® to Secure FPGA Contents
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
IGLOO Product Family
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X1, and
LVCMOS 2.5 V / 5.0 V Input1
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-
LVDS (AGL250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate1 and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the IGLOO Family
Clock Conditioning Circuit (CCC) and PLL1
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay
Capabilities, and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Embedded Memory
1SRkAbMitsoafnFdlasFhIFROOsMwUithserVaNroianbvloe-laAtsipleecMt-eRmatoiory4,608-Bit1 RAM
Blocks (×1, ×2, ×4, ×9,
True Dual-Port SRAM
a(enxdce×p1t8×o1r8g)a1nizations)
ARM Processor Support in IGLOO FPGAs
• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available
with or without Debug
IGLOO Devices
AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000
ARM-Enabled IGLOO Devices
M1AGL250 M1AGL400 M1AGL600 M1AGL1000
System Gates
15 k
30 k
60 k 125 k 250 k
400 k
600 k
1M
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
Flash*Freeze Mode (typical, µW)
RAM kbits (1,024 bits)
128
384
5
256 512 1,024 2,048 –
768
1,536 3,072
6,144
9,216
13,824
24,576
5
10 16
24
32
36
53
18 36
36
54 108
144
4,608-Bit Blocks
48
8
12 24
32
FlashROM Bits
Secure (AES) ISP 1
Integrated PLL in CCCs 2
VersaNet Globals 3
I/O Banks
Maximum User I/Os
1k
1k
1k 1k
1k
1k
1k
1k
Yes Yes
Yes
Yes
Yes
Yes
11
1
1
1
1
6
6
18 18
18
18
18
18
2
2
22
4
4
4
4
49
81
96 133 143 194 235
300
Package Pins
UC/CS
QFN
VQFP
FBGA
QN68
UC81/CS81
QN48, QN68,
QN132
VQ100
CS121
QN132
VQ100
FG144 5
CS196
QN132
VQ100
FG144
CS196 4
QN132 4,5
VQ100
FG144
CS196
FG144,
FG256,
FG484
CS281
FG144,
FG256,
FG484
CS281
FG144,
FG256,
FG484
Notes:
1. AES is not available for ARM-enabled IGLOO devices.
2. AGL060 in CS121 does not support the PLL.
3. Six chip (main) and twelve quadrant global networks are available for AGL060 and above.
4. The M1AGL250 device does not support this package.
5. Device/package support TBD
6. For higher densities and support of additional features, refer to the IGLOOe Low-Power Flash FPGAs with Flash*Freeze
Technology handbook.
1 AGL015 and AGL030 devices do not support this feature.
‡ Supported only by AGL015 and AGL030 devices.
December 2008
© 2008 Actel Corporation
I






AGL125 Datasheet, Funktion
IGLOO Device Family Overview
www.DataSheet4U.com
Flash Advantages
Low Power
Flash-based IGLOO devices exhibit power characteristics similar to those of an ASIC, making them
an ideal choice for power-sensitive applications. IGLOO devices have only a very limited power-on
current surge and no high-current transition period, both of which occur on many FPGAs.
IGLOO devices also have low dynamic power consumption to further maximize power savings;
power is even further reduced by the use of a 1.2 V core voltage.
Low dynamic power consumption, combined with low static power consumption and Flash*Freeze
technology, gives the IGLOO device the lowest total system power offered by any FPGA.
Security
The nonvolatile, flash-based IGLOO devices do not require a boot PROM, so there is no vulnerable
external bitstream that can be easily copied. IGLOO devices incorporate FlashLock, which provides a
unique combination of reprogrammability and design security without external overhead,
advantages that only an FPGA with nonvolatile flash programming can offer.
IGLOO devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed
intellectual property and configuration data. In addition, all FlashROM data in IGLOO devices can
be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher
encryption standard. AES was adopted by the National Institute of Standards and Technology
(NIST) in 2000 and replaces the 1977 DES standard. IGLOO devices have a built-in AES decryption
engine and a flash-based AES key that make them the most comprehensive programmable logic
device security solution available today. IGLOO devices with AES-based security allow for secure,
remote field updates over public networks such as the Internet, and ensure that valuable IP
remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a
programmed IGLOO device cannot be read back, although secure design verification is possible.
Security, built into the FPGA fabric, is an inherent component of the IGLOO family. The flash cells
are located beneath seven metal layers, and many device design and layout techniques have been
used to make invasive attacks extremely difficult. The IGLOO family, with FlashLock and AES
security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable
IP is protected and secure, making remote ISP possible. An IGLOO device provides the most
impenetrable security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed,
the configuration data is an inherent part of the FPGA structure, and no external configuration
data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based
IGLOO FPGAs do not require system configuration components such as EEPROMs or
microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB
area, and increases security and system reliability.
Live at Power-Up
The Actel flash-based IGLOO devices support Level 0 of the LAPU classification standard. This
feature helps in system component initialization, execution of critical tasks before the processor
wakes up, setup and configuration of memory blocks, clock generation, and bus activity
management. The LAPU feature of flash-based IGLOO devices greatly simplifies total system design
and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In
addition, glitches and brownouts in system power will not corrupt the IGLOO device's flash
configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system
power is restored. This enables the reduction or complete removal of the configuration PROM,
expensive voltage monitor, brownout detection, and clock generator devices from the PCB design.
Flash-based IGLOO devices simplify total system design and reduce cost and design risk while
increasing system reliability and improving system initialization time.
IGLOO flash FPGAs allow the user to quickly enter and exit Flash*Freeze mode. This is done almost
instantly (within 1 µs) and the device retains configuration and data in registers and RAM. Unlike
SRAM-based FPGAs the device does not need to reload configuration and design state from
1-2 v1.3

6 Page









AGL125 pdf, datenblatt
IGLOO Device Family Overview
Part Number and Revision Date
Part Number 51700095-001-6
Revised December 2008
www.DataSheet4U.com
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous Version
Changes in Current Version (v1.3)
v1.2 QN48 and QN68 were added to the AGL030 for the following tables:
(October 2008) "IGLOO Product Family"
"IGLOO Ordering Information"
"Temperature Grade Offerings"
QN132 is fully supported by AGL125 so footnote 3 was removed.
v1.1
(July 2008)
This document was updated to include AGL400 device information. The following
sections were updated:
"IGLOO Product Family"
"IGLOO Ordering Information"
"Temperature Grade Offerings"
"IGLOO Product Family"
Figure 1-2 · IGLOO Device Architecture Overview with Four I/O Banks (AGL250,
AGL600, AGL400, and AGL1000)
v1.0
(March 2008)
As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core
voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to
1.5 V.
51700095-001-3
(March 2008)
This document was divided into two sections and given a version number, starting
at v1.0. The first section of the document includes features, benefits, ordering
information, and temperature and speed grade offerings. The second section is a
device family overview.
51700095-001-2 The "Low Power" section was updated to change "1.2 V and 1.5 V Core Voltage"
(February 2008) to "1.2 V and 1.5 V Core and I/O Voltage." The text "(from 12 µW)" was removed
from "Low-Power Active FPGA Operation."
1.2_V was added to the list of core and I/O voltages in the "Advanced I/O" and
"I/Os with Advanced I/O Standards" sections.
The "Embedded Memory" section was updated to remove the footnote reference
from the section heading and place it instead after "4,608-Bit" and "True Dual-Port
SRAM (except ×18)."
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