ADIS16305 Datasheet PDF - Analog Devices
| Part Number | ADIS16305 | |
| Description | Precision Four Degrees Of Freedom Sensor | |
| Manufacturers | Analog Devices | |
| Logo |  |
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Precision Four Degrees of Freedom Sensor
ADIS16305
FEATURES
Digital gyroscope with range scaling
±75°/sec, ±150°/sec, ±300°/sec settings
Triaxis digital accelerometer: ±3 g
Wide sensor bandwidth: 330 Hz
Autonomous operation and data collection
No external configuration commands required
Start-up time: 180 ms
Sleep mode recovery time: 4 ms
Factory-calibrated sensitivity, bias, and alignment
Calibration temperature range: −40°C to +85°C
SPI-compatible serial interface
Embedded temperature sensor
Programmable operation and control
Automatic and manual bias correction controls
Bartlett window FIR filter length, number of taps
Digital I/O: data-ready, alarm indicator, general-purpose
Alarms for condition monitoring
Sleep mode for power management
DAC output voltage
Enable external sample clock input: up to 1.2 kHz
Single-command self-test
Single-supply operation: 4.75 V to 5.25 V
2000 g shock survivability
Operating temperature range: −40°C to +85°C
APPLICATIONS
Medical instrumentation
Robotics
Platform controls
Navigation
GENERAL DESCRIPTION
The iSensor® ADIS16305 is a complete inertial system that
includes a gyroscope and triaxis accelerometer. Each sensor in
the ADIS16305 combines industry-leading iMEMS® technology
with signal conditioning that optimizes dynamic performance.
The factory calibration characterizes each sensor for sensitivity,
bias, alignment, and linear acceleration (gyro bias). As a result, each
sensor has its own dynamic compensation formulas that provide
accurate sensor measurements over a variety of conditions.
The ADIS16305 provides a simple, cost-effective method for
integrating accurate, multiaxis, inertial sensing into industrial
systems, especially when compared with the complexity and
investment associated with discrete designs. All necessary motion
FUNCTIONAL BLOCK DIAGRAM
AUX_
ADC
AUX_
DAC
TEMPERATURE
SENSOR
MEMS
ANGULAR RATE
SENSOR
TRIAXIS MEMS
ACCELERATION
SENSOR
SIGNAL
CONDITIONING
AND
CONVERSION
CALIBRATION
AND
DIGITAL
PROCESSING
OUTPUT
REGISTERS
AND SPI
INTERFACE
SELF-TEST
ADIS16305
ALARMS
DIGITAL
CONTROL
POWER
MANAGEMENT
RST DIO1 DIO2 DIO3 DIO4
Figure 1.
CS
SCLK
DIN
DOUT
VCC
GND
testing and calibration are part of the production process at the
factory, greatly reducing system integration time. Tight orthogonal
alignment simplifies inertial frame alignment in navigation systems.
An improved SPI interface and register structure provide faster data
collection and configuration control. The ADIS16305 uses a pinout
that is compatible with the ADIS1635x, ADIS1636x, and
ADIS1640x families, when used with an interface flex connector.
This compact module is approximately 23 mm × 31 mm × 8 mm
and provides a standard connector interface, which enables
horizontal or vertical mounting.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
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ADIS16305www.DataSheet4U.com
TIMING SPECIFICATIONS
TA = 25°C, VCC = 5 V, unless otherwise noted.
Table 2.
Parameter
fSCLK
tSTALL
tREADRATE
tCS
tDAV
tDSU
tDHD
tSCLKR, tSCLKF
tDR, tDF
tSFS
t1
tx
t2
t3
Description
Serial clock
Stall period between data
Read rate
Chip select to clock edge
DOUT valid after SCLK edge
DIN setup time before SCLK rising edge
DIN hold time after SCLK rising edge
SCLK rise/fall times (not shown in figures)
DOUT rise/fall times (not shown in figures)
CS high after SCLK edge
Input sync positive pulse width
Input sync low time
Input sync to data-ready output
Input sync period
Normal Mode
(SMPL_PRD ≤ 0x09)
Min1 Typ Max
0.01 2.0
9
40
48.8
24.4
48.8
5
5
5
100
12.5
12.5
5
100
600
833
Low Power Mode
(SMPL_PRD ≥ 0x0A)
Min1 Typ Max
0.01 0.3
75
100
48.8
24.4
48.8
5
5
5
100
12.5
12.5
Burst Read
Min1 Typ Max
0.01 1.0
1/fSCLK
48.8
100
24.4
48.8
5 12.5
5 12.5
5
5
100
600
833
Unit
MHz
μs
μs
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
μs
1 Guaranteed by design and characterization, but not tested in production.
Timing Diagrams
CS
SCLK
DOUT
DIN
tCS
1
MSB
R/W
23
4
56
tDAV
DB14
tDSU
DB13
DB12
tDHD
DB11
DB10
A6 A5 A4 A3 A2
Figure 2. SPI Timing and Sequence
15 16
tSFS
DB2
DB1 LSB
D2 D1 LSB
tREADRATE
tSTALL
CS
SCLK
Figure 3. Stall Time and Data Rate
SYNC
CLOCK (DIO4)
DATA
READY
t3
t1 tX
t2
Figure 4. Input Clock Timing Diagram
Rev. 0 | Page 5 of 20
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| Information | Total 20 Pages | |
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