|
|
PDF ADP2140 Data sheet ( Hoja de datos )
| Número de pieza | ADP2140 | |
| Descripción | Low Quiescent Current Buck | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ADP2140 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
3 MHz, 600 mA, Low Quiescent Currentwww.DataSheet4U.com
Buck with 300 mA LDO Regulator
ADP2140
FEATURES
Input voltage range: 2.3 V to 5.5 V
LDO input (VIN2) 1.65 V to 5.5 V
Buck output voltage range: 1.0 V to 3.3 V
LDO output voltage range: 0.8 V to 3.3 V
Buck output current: 600 mA
LDO output current: 300 mA
LDO quiescent current: 22 μA with zero load
Buck quiescent current: 20 μA in PSM mode
Low shutdown current: <0.3 μA
Low LDO dropout 110 mV @ 300 mA load
High LDO PSRR
65 dB @ 10 kHz at VOUT2 = 1.2 V
55 dB @ 100 kHz at VOUT2 = 1.2 V
Low noise LDO: 40 μV rms at VOUT2 = 1.2 V
Initial accuracy: ±1%
Current-limit and thermal overload protection
Power-good indicator
Optional enable sequencing
10-lead 0.75 mm × 3 mm × 3 mm LFCSP package
APPLICATIONS
Mobile phones
Personal media players
Digital camera and audio devices
Portable and battery-powered equipment
GENERAL DESCRIPTION
The ADP2140 includes a high efficiency, low quiescent 600 mA
stepdown dc-to-dc converter and a 300 mA LDO packaged in a
small 10-lead 3 mm × 3 mm LFCSP. The total solution requires
only four tiny external components.
The buck regulator uses a proprietary high speed current-mode,
constant frequency, pulse-width modulation (PWM) control
scheme for excellent stability and transient response. To ensure
the longest battery life in portable applications, the ADP2140 has
a power saving variable frequency mode to reduce switching fre-
quency under light loads.
The LDO is a low quiescent current, low dropout linear regulator
designed to operate in a split supply mode with VIN2 as low as
1.65 V. The low input voltage minimum allows the LDO to be
powered from the output of the buck regulator increasing effi-
ciency and reducing power dissipation. The ADP2140 runs from
input voltages of 2.3 V to 5.5 V allowing single Li+/Li− polymer
TYPICAL APPLICATION CIRCUITS
VIN1 = 3.6V
CIN +
100kΩ 10µF
10
PG
EN1
EN2
VOUT2 = 1.8V
COUT2 +
1µF
9
8
7
6
ADP2140
VIN1 PGND
PG SW
EN1 AGND
EN2 FB
VOUT2 VIN2
1
2
3
4
5
1µH VOUT = 1.2V
+ COUT
10µF
Figure 1. ADP2140 with LDO Connected to VIN1
VIN1 = 3.3V
CIN +
100kΩ 10µF
10
PG
EN1
EN2
VOUT2 = 1.2V
COUT2 +
1µF
9
8
7
6
ADP2140
VIN1 PGND
PG SW
EN1
AGND
EN2 FB
VOUT2 VIN2
1
2
3
4
5
1µH VOUT = 1.8V
+ COUT
10µF
Figure 2. ADP2140 with LDO Connected to Buck Output
cell, multiple alkaline/NiMH cell, PCMCIA, and other standard
power sources.
ADP2140 includes a power-good pin, soft start, and internal
compensation. Numerous power sequencing options are user-
selectable through two enable inputs. In autosequencing mode,
the highest voltage output enables on the rising edge of EN1.
During logic controlled shutdown, the input disconnects from
the output and draws less than 300 nA from the input source.
Other key features include: undervoltage lockout to prevent deep
battery discharge, soft start to prevent input current overshoot
at startup, and both short-circuit protection and thermal overload
protection circuits to prevent damage in adverse conditions.
When the ADP2140 is used with two 0603 capacitors, one 0402
capacitor, one 0402 resistor, and one 0805 chip inductor, the total
solution size is approximately 90 mm2 resulting in the smallest foot-
print solution to meet a variety of portable applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN1, VIN2 to PGND, AGND
VOUT2 to PGND, AGND
SW to PGND, AGND
FB to PGND, AGND
PG to PGND, AGND
EN1, EN2 to PGND, AGND
Storage Temperature Range
Operating Ambient Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
−0.3 V to +6.5 V
−0.3 V to VIN2
−0.3 V to VIN1
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−65°C to +150°C
−40°C to +85°C
−40°C to +125°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in com-
bination. The ADP2140 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that TJ is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
need to be derated.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long as
the junction temperature is within specification limits. The
junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction-to-ambient thermal resistance of the
package (θJA).
Maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) using the
formula
TJ = TA + (PD × θJA)
ADP2140www.DataSheet4U.com
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4 in. × 3 in. circuit
board. Refer to JESD 51-7 for detailed information on the board
construction.
For more information, see AN-772 Application Note, A Design
and Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP).
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12, Guidelines for
Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as thermal
resistances. ΨJB measures the component power flowing through
multiple thermal paths rather than a single path, as in thermal
resistance, θJB. Therefore, ΨJB thermal paths include convection
from the top of the package as well as radiation from the package,
factors that make ΨJB more useful in real-world applications.
Maximum junction temperature (TJ) is calculated from the
board temperature (TB) and power dissipation (PD) using the
formula
TJ = TB + (PD × ΨJB)
Refer to JESD51-8 and JESD51-12 for more detailed
information about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
10-Lead 3 mm × 3 mm LFCSP
θJA ΨJB Unit
35.3 16.9 °C/W
ESD CAUTION
Rev. 0 | Page 5 of 32
5 Page 
ADP2140www.DataSheet4U.com
VIN1 = 4 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 10 μF, TA = 25°C, unless otherwise noted.
T
SWITCH NODE
T
33
SWITCH NODE
LOAD CURRENT
LOAD CURRENT
1
2
OUTPUT VOLTAGE
CH1 50.0mA CH2 50.0mV M20.0µs
CH3 5.00V
T 10.40%
A CH1 51.0mA
Figure 28. Load Transient, VOUT = 1.8 V,10 mA to 110 mA, Load Current Rise
Time = 200 ns
T
SWITCH NODE
3
LOAD CURRENT
1
2
OUTPUT VOLTAGE
CH1 50.0mA CH2 100.0mV M20.0µs
CH3 5.00V
T 10.40%
A CH1 50.0mA
Figure 31. Load Transient, VOUT = 3.3 V,10 mA to 110 mA, Load Current Rise
Time = 200 ns
T
SWITCH NODE
3
LOAD CURRENT
1
2
OUTPUT VOLTAGE
CH1 200mA CH2 100.0mV M20.0µs
CH3 5.00V
T 10.40%
A CH1 292mA
Figure 29. Load Transient, VOUT = 3.3 V, 200 mA to 600 mA, Load Current Rise
Time = 200 ns
T
SWITCH NODE
3
LOAD CURRENT
1
2
OUTPUT VOLTAGE
CH1 100mA CH2 100.0mV M20.0µs
CH3 5.00V
T 10.40%
A CH1 80.0mA
Figure 30. Load Transient, VOUT = 3.3 V, 50 mA to 250 mA, Load Current Rise
Time = 200 ns
1
2
OUTPUT VOLTAGE
CH1 200.0mA CH2 50.0mV M20.0µs
CH3 5.00V
T 10.40%
A CH1 376mA
Figure 32. Load Transient, VOUT = 1.2 V, 200 mA to 600 mA, Load Current Rise
Time = 200 ns
T
3
SWITCH NODE
LOAD CURRENT
1
2
OUTPUT VOLTAGE
CH1 100.0mA CH2 50.0mV M20.0µs
CH3 5.00V
T 10.40%
A CH1 154mA
Figure 33. Load Transient, VOUT = 1.2 V, 50 mA to 250 mA, Load Current Rise
Time = 200 ns
Rev. 0 | Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADP2140.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ADP2140 | Low Quiescent Current Buck | Analog Devices |
| ADP2147 | Buck Regulator | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |