CAT25128 Datasheet PDF - ON Semiconductor
| Part Number | CAT25128 | |
| Description | 128-Kb SPI Serial CMOS EEPROM | |
| Manufacturers | ON Semiconductor | |
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CAT25128
128-Kb SPI Serial CMOS
EEPROM
Description
The CAT25128 is a 128−Kb Serial CMOS EEPROM device
internally organized as 16Kx8 bits. This features a 64−byte page write
buffer and supports the Serial Peripheral Interface (SPI) protocol. The
device is enabled through a Chip Select (CS) input. In addition, the
required bus signals are clock input (SCK), data input (SI) and data
output (SO) lines. The HOLD input may be used to pause any serial
communication with the CAT25128 device. The device features
software and hardware write protection, including partial as well as
full array protection.
On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.*
Features
• 20 MHz SPI Compatible
• 1.8 V to 5.5 V Supply Voltage Range
• SPI Modes (0,0) & (1,1)
• 64−byte Page Write Buffer
• Additional Identification Page with Permanent Write Protection
• Self−timed Write Cycle
• Hardware and Software Protection
• Block Write Protection
− Protect 1/4, 1/2 or Entire EEPROM Array
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• Industrial and Extended Temperature Range
• 8−lead PDIP, SOIC, TSSOP and 8−pad TDFN, UDFN Packages
• This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
VCC
SI
CS
WP
HOLD
SCK
CAT25128
SO
VSS
Figure 1. Functional Symbol
* Available for New Product (Rev. E)
© Semiconductor Components Industries, LLC, 2014
February, 2014 − Rev. 8
1
http://onsemi.com
SOIC−8
V SUFFIX
CASE 751BD
TDFN−8**
VP2 SUFFIX
CASE 511AK
UDFN−8
HU4 SUFFIX
CASE 517AZ
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
SOIC−8
X SUFFIX
CASE 751BE
PIN CONFIGURATION
CS 1
SO
VCC
HOLD
WP SCK
VSS SI
PDIP (L), SOIC (X, V),
TSSOP (Y), TDFN** (VP2), UDFN (HU4)
** The TDFN−8 (VP2) package is not recommended
for new designs.
PIN FUNCTION
Pin Name†
Function
CS Chip Select
SO Serial Data Output
WP Write Protect
VSS Ground
SI Serial Data Input
SCK
Serial Clock
HOLD
Hold Transmission Input
VCC Power Supply
†The exposed pad for the TDFN/UDFN packages can
be left floating or connected to Ground.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 19 of this data sheet.
Publication Order Number:
CAT25128/D
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CAT25128
Table 8. A.C. CHARACTERISTICS – NEW PRODUCT (Rev E) (VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C (Industrial) and
VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) (Note 11)
VCC = 1.8 V − 5.5 V
−405C to +855C
VCC = 2.5 V − 5.5 V
−405C to +1255C
VCC = 4.5 V − 5.5 V
−405C to +855C
Symbol
Parameter
Min Max Min Max Min
fSCK
Clock Frequency
DC 5 DC 10 DC
tSU Data Setup Time 20 10
5
tH Data Hold Time
20 10
5
tWH SCK High Time
75 40
20
tWL SCK Low Time
75 40
20
tLZ HOLD to Output Low Z
50 25
tRI (Note 12)
Input Rise Time
22
tFI (Note 12)
Input Fall Time
22
tHD HOLD Setup Time
0
0
0
tCD HOLD Hold Time
10
10
5
tV Output Valid from Clock Low
75 40
tHO Output Hold Time
0
0
0
tDIS Output Disable Time
50 20
tHZ HOLD to Output High Z
100 25
tCS CS High Time
80 40
20
tCSS
CS Setup Time
30 30
15
tCSH
CS Hold Time
30 30
20
tCNS
CS Inactive Setup Time
20
20
15
tCNH
CS Inactive Hold Time
20
20
15
tWPS
WP Setup Time
10 10
10
tWPH
WP Hold Time
10 10
10
tWC (Note 13) Write Cycle Time
55
11. AC Test Conditions:
Input Pulse Voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 VCC
Output load: current source IOL max/IOH max; CL = 30 pF
12. This parameter is tested initially and after a design or process change that affects the parameter.
13. tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
Max Units
20 MHz
ns
ns
ns
ns
25 ns
2 ms
2 ms
ns
ns
20 ns
ns
20 ns
25 ns
ns
ns
ns
ns
ns
ns
ns
5 ms
Table 9. POWER−UP TIMING (Notes 12, 14)
Symbol
Parameter
Min Max Units
tPUR
Power−up to Read Operation
0.1 1
tPUW
Power−up to Write Operation
0.1 1
14. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
ms
ms
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