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PDF CAT5419 Data sheet ( Hoja de datos )
| Número de pieza | CAT5419 | |
| Descripción | Dual Digital Potentiometer | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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CAT5419
Dual Digital
Potentiometer (POT)
with 64 Taps
and 2‐wire Interface
Description
The CAT5419 is two digital POTs integrated with control logic and
16 bytes of NVRAM memory.
A separate 6-bit control register (WCR) independently controls the
wiper tap position for each digital POT. Associated with each wiper
control register are four 6-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the wiper control
register or any of the non-volatile data registers is via a 2-wire serial
bus (I2C-like). On power-up, the contents of the first data register
(DR0) for each of the two potentiometers is automatically loaded into
its respective wiper control registers (WCR).
The Write Protection (WP) pin protects against inadvertent
programming of the data register.
The CAT5419 can be used as a potentiometer or as a two terminal,
variable resistor. It is intended for circuit level or system level
adjustments in a wide variety of applications.
Features
Two Linear-taper Digital Potentiometers
64 Resistor Taps per Potentiometer
End to End Resistance 2.5 kW, 10 kW, 50 kW or 100 kW
Potentiometer Control and Memory Access via 2-wire Interface
(I2C like)
Low Wiper Resistance, Typically 80 W
Four Non-volatile Wiper Settings for Each Potentiometer
Recall of Wiper Settings at Power Up
2.5 to 6.0 Volt Operation
Standby Current less than 1 mA
1,000,000 Nonvolatile WRITE Cycles
100 Year Nonvolatile Memory Data Retention
24-lead SOIC and 24-lead TSSOP
Write Protection for Data Register
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
http://onsemi.com
TSSOP24
Y SUFFIX
CASE 948AR
SOIC−24
W SUFFIX
CASE 751BK
PIN CONNECTIONS
VCC
RL0
RH0
RW0
A2
WP
SDA
A1
RL1
RH1
RW1
GND
1
CAT5419
SOIC−24 (W)
(Top View)
NC
NC
NC
NC
A0
NC
A3
SCL
NC
NC
NC
NC
SDA
A1
RL1
RH1
RW1
GND
NC
NC
NC
NC
SCL
A3
1
CAT5419
TSSOP24 (Y)
(Top View)
WP
A2
RW0
RH0
RL0
VCC
NC
NC
NC
NC
A0
NC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
Semiconductor Components Industries, LLC, 2013
July, 2013 − Rev. 11
1
Publication Order Number:
CAT5419/D
1 page  
CAT5419
Table 7. A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min Typ
fSCL
TI (Note 8)
tAA
tBUF (Note 8)
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR (Note 8)
tF (Note 8)
tSU:STO
tDH
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the bus must be free before a new transmission can start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1.2
0.6
1.2
0.6
0.6
0
100
0.6
50
Max Units
400 kHz
50 ns
0.9 ms
ms
ms
ms
ms
ms
ns
ns
0.3 ms
300 ns
ms
ns
Table 8. POWER UP TIMING (Note 8) (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min Typ
tPUR
Power-up to Read Operation
tPUW
Power-up to Write Operation
8. This parameter is tested initially and after a design or process change that affects the parameter.
Max Units
1 ms
1 ms
Table 9. WRITE CYCLES LIMITS (Note 9)
Symbol
Parameter
Max Units
tWR Write Cycle Time
5 ms
9. The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Table 10. RELIABILITY CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Reference Test Method
Min Typ Max
NEND (Note 10)
Endurance
MIL−STD−883, Test Method 1033
1,000,000
TDR (Note 10)
Data Retention
MIL−STD−883, Test Method 1008
100
VZAP (Note 10)
ESD Susceptibility MIL−STD−883, Test Method 3015
2,000
ILTH (Notes 10, 11)
Latch-up
JEDEC Standard 17
100
10. This parameter is tested initially and after a design or process change that affects the parameter.
11. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Units
Cycles/Byte
Years
Volts
mA
http://onsemi.com
5
5 Page 
CAT5419
SDA
0101
S ID3 ID2 ID1 ID0 A3 A2 A1 A0
T
A
R
Device ID
T
Internal
Address
A
C
K
I3 I2 I1 I0
Instruction
Opcode
R1 R0
Register
Address
0
P0
A
CK
Pot/WCR
Address
Figure 10. Two-byte Instruction Sequence
S
T
O
P
SDA
0 101
S
T
A
R
T
ID3 ID2 ID1 ID0 A3 A2 A1 A0
Device ID
Internal
Address
ACK
I3 I2 I1 I0
Instruction
Opcode
R1 R0 0 P0 CAK
Data Pot/WCR
Register Address
Address
D7 D6 D5 D4 D3 D2 D1 D0
WCR[7:0]
or
Data Register D[7:0]
AS
CT
KO
P
Figure 11. Three-byte Instruction Sequence
SDA
0101
S ID3 ID2 ID1 ID0 A3 A2 A1 A0
AT Device ID
R
Internal
Address
T
A
CK
I3 I2 I1 I0
Instruction
Opcode
R1 R0
0
P0
A
C
Data
Register
Pot/WCR
Address
K
Address
I
N
C
1
I
N
C
2
Figure 12. Increment/Decrement Instruction Sequence
ID
N
C
E
C
n1
D
E
C
n
S
T
O
P
INC/DEC
Command
Issued
SCL
SDA
RW
tWRID
Voltage Out
Figure 13. Increment/Decrement Timing Limits
http://onsemi.com
11
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| PDF Descargar | [ Datasheet CAT5419.PDF ] | |
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