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PDF CAT5409 Data sheet ( Hoja de datos )
| Número de pieza | CAT5409 | |
| Descripción | Quad Digital Potentiometer | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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CAT5409
Quad Digital
Potentiometer (POT)
with 64 Taps
and I2C Interface
Description
The CAT5409 is four digital POTs integrated with control logic and
16 bytes of NVRAM memory.
A separate 6-bit control register (WCR) independently controls the
wiper tap position for each digital POT. Associated with each wiper
control register are four 6-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the wiper control
register or any of the non-volatile data registers is via a I2C serial bus.
On power-up, the contents of the first data register (DR0) for each of
the four potentiometers is automatically loaded into its respective
wiper control register (WCR).
The Write Protection (WP) pin protects against inadvertent
programming of the data register.
The CAT5409 can be used as a potentiometer or as a two terminal,
variable resistor. It is intended for circuit level or system level
adjustments in a wide variety of applications.
Features
Four Linear Taper Digital Potentiometers
64 Resistor Taps per Potentiometer
End to End Resistance 2.5 kW, 10 kW, 50 kW or 100 kW
I2C Interface
Low Wiper Resistance, Typically 80 W
Four Non-volatile Wiper Settings for Each Potentiometer
Recall of Saved Wiper Settings at Power-up
2.5 to 6.0 Volt Operation
Standby Current less than 1 mA
1,000,000 Nonvolatile WRITE Cycles
100 Year Nonvolatile Memory Data Retention
24-lead SOIC and 24-lead TSSOP
Write Protection for Data Register
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
http://onsemi.com
TSSOP24
Y SUFFIX
CASE 948AR
SOIC−24
W SUFFIX
CASE 751BK
VCC
RL0
RH0
RW0
A2
WP
SDA
A1
RL1
RH1
RW1
GND
PIN CONNECTIONS
1
CAT5409
SOIC−24 (W)
(Top View)
NC
RL3
RH3
RW3
A0
NC
A3
SCL
RL2
RH2
RW2
NC
SDA
A1
RL1
RH1
RW1
GND
NC
RW2
RH2
RL2
SCL
A3
1
CAT5409
TSSOP−24 (Y)
(Top View)
WP
A2
RW0
RH0
RL0
VCC
NC
RL3
RH3
RW3
A0
NC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
Semiconductor Components Industries, LLC, 2013
July, 2013 − Rev. 15
1
Publication Order Number:
CAT5409/D
1 page  
CAT5409
Table 5. D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Test Conditions
Min Max
ICC
ISB
ILI
ILO
VIL
VIH
VOL1
Power Supply Current
Standby Current (VCC = 5 V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (VCC = 3 V)
fSCL = 400 kHz
VIN = GND or VCC, SDA Open
VIN = GND to VCC
VOUT = GND to VCC
IOL = 3 mA
−1
VCC x 0.7
1
1
10
10
VCC x 0.3
VCC + 1.0
0.4
Units
mA
mA
mA
mA
V
V
V
Table 6. CAPACITANCE (Note 8) (TA = 25C, f = 1.0 MHz, VCC = 5 V)
Symbol
Test
Conditions
CI/O Input/Output Capacitance (SDA)
VI/O = 0 V
CIN Input Capacitance (A0, A1, A2, A3, SCL, WP)
VIN = 0 V
8. This parameter is tested initially and after a design or process change that affects the parameter.
Table 7. A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min Typ
fSCL
TI (Note 10)
tAA
tBUF (Note 10)
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR (Note 10)
tF (Note 10)
tSU:STO
tDH
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the bus must be free before a new transmission can start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition SetupTime (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1.2
0.6
1.2
0.6
0.6
0
100
0.6
50
Max
8
6
Max
400
50
0.9
0.3
300
Units
pF
pF
Units
kHz
ns
ms
ms
ms
ms
ms
ms
ns
ns
ms
ns
ms
ns
Table 8. POWER UP TIMING (Note 10)
Symbol
tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
Parameter
Max Units
1 ms
1 ms
Table 9. WRITE CYCLE LIMITS (Note 9)
Symbol
Parameter
Max Units
tWR Write Cycle Time
5 ms
9. The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
http://onsemi.com
5
5 Page 
CAT5409
SDA
010 1
S ID3 ID2 ID1 ID0 A3 A2 A1 A0
T
A
R
Device ID
T
Internal
Address
CA
K
I3 I2 I1 I0
Instruction
Opcode
R1 R0 P1 P0 CAK
Register Pot/WCR
Address Address
S
T
O
P
Figure 10. Two-byte Instruction Sequence
SDA
0 101
S
T
A
R
T
ID3 ID2 ID1 ID0 A3 A2 A1 A0
Device ID
Internal
Address
A
C
K
I3 I2 I1 I0
Instruction
Opcode
R1 R0 P1 P0
Data Pot/WCR
Register Address
CAK
D7 D6 D5 D4 D3 D2 D1 D0
WCR[7:0]
or
Data Register D[7:0]
CAK
S
T
O
P
Address
Figure 11. Three-byte Instruction Sequence
SDA
0101
S ID3 ID2 ID1 ID0 A3 A2 A1 A0 A I3 I2 I1 I0 R1 R0 P1 P0 A I I
AT Device ID
R
T
Internal
Address
C
K
Instruction
Opcode
C
Data
Register
Pot/WCR
Address
K
NC
1
NC
2
Address
Figure 12. Increment/Decrement Instruction Sequence
I
NC
n
D
CE
1
D
CE
n
S
OT
P
INC/DEC
Command
Issued
SCL
SDA
tWRID
Voltage Out
RW
Figure 13. Increment/Decrement Timing Limits
http://onsemi.com
11
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| PDF Descargar | [ Datasheet CAT5409.PDF ] | |
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