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CAT1640 Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer CAT1640
Beschreibung Supervisory Circuits with I2C Serial 64K CMOS EEPROM
Hersteller ON Semiconductor
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Gesamt 18 Seiten
CAT1640 Datasheet, Funktion
CAT1640w,wwC.DaAtaSThee1t4U6.co4m1
Supervisory Circuits with I2C Serial 64K
ALOGEN FR
CMOS EEPROM
LEA D F REETM
FEATURES
s Precision power supply voltage monitor
— 5V, 3.3V and 3V systems
- +5.0V (+/- 5%, +/- 10%)
- +3.3V (+/- 5%, +/- 10%)
- +3.0V (+/- 10%)
s Active low reset, CAT1640
s Active high reset, CAT1641
s Valid reset guaranteed at VCC=1V
s 400kHz I2C bus
s 3.0V to 5.5V operation
s Low power CMOS technology
s 64-Byte page write buffer
s 1,000,000 Program/Erase cycles
s 100 year data retention
s 8-pin DIP, SOIC, TSSOP and TDFN packages
s Industrial temperature range
DESCRIPTION
The CAT1640 and CAT1641 are complete memory and
supervisory solutions for microcontroller-based systems.
A 64kbit serial EEPROM memory and a system power
supervisor with brown-out protection are integrated
together in low power CMOS technology. Memory
interface is via a 400kHz I2C bus.
The CAT1640 provides a precision VCC sense circuit
and drives an open drain output, RESET low whenever
VCC falls below the reset threshold voltage.
The CAT1641 provides a precision VCC sense circuit
that drives an open drain output, RESET high whenever
VCC falls below the reset threshold voltage.
The power supply monitor and reset circuit protect
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
voltages support 5V, 3.3V and 3V systems. If power
supply voltages are out of tolerance reset signals become
active, preventing the system microcontroller, ASIC or
peripherals from operating. Reset signals become inactive
typically 200 ms after the supply voltage exceeds the reset
threshold level. With both active high and low reset options,
interface to microcontrollers and other ICs is simple. In
addition, the RESET (CAT1640) pin can be used as an
input for push-button manual reset capability.
The CAT1640/41 memory features a 64-byte page. In
addition, hardware data protection is provided by a VCC
sense circuit that prevents writes to memory whenever VCC
falls below the reset threshold or until VCC reaches the reset
threshold during power up.
Available packages include an 8-pin DIP, SOIC, TSSOP
and 4.9 x 3mm TDFN.
PIN CONFIGURATION
PDIP (L) SOIC (W)
A0 1
A1 2
A2 3
VSS 4
CAT1640
8 VCC
7 RESET
6 SCL
5 SDA
A0 1
A1 2
A2 3
VSS 4
TSSOP (Y)
CAT1640
8 VCC
7 RESET
6 SCL
5 SDA
TDFN PACKAGE: 4.9MM X 3MM
(ZD2)
A0 1
A1 2
A2 3
VSS 4
CAT1640
8 VCC
7 RESET
6 SCL
5 SDA
A0 1
A1 2
A2 3
VSS 4
CAT1641
8 VCC
7 RESET
6 SCL
5 SDA
A0 1
A1 2
A2 3
VSS 4
CAT1641
8 VCC
7 RESET
6 SCL
5 SDA
A0 1
A1 2
A2 3
VSS 4
CAT1641
8 VCC
7 RESET
6 SCL
5 SDA
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice.
1
Doc. No. MD-3012, Rev. D






CAT1640 Datasheet, Funktion
CAT1640, CAT1641
www.DataSheet4U.com
DEVICE OPERATION
Reset Controller Description
The CAT1640/41 precision RESET controllers ensure
correct system operation during brownout and power
up/down conditions. They are configured with open-
drain RESET/RESET outputs.
During power-up, the RESET/RESET output remains
active until VCC reaches the VTH threshold and will
continue driving the outputs for approximately 200ms
(tPURST) after reaching VTH. After the tPURST timeout
interval, the device will cease to drive the reset output.
At this point the reset output will be pulled up or down by
their respective pull up/down resistors.
During power-down, the RESET/RESET output will be
active when VCC falls below VTH. The RESET/RESET
output will be valid so long as VCC is >1.0V (VRVALID).
The device is designed to ignore the fast negative going
VCC transient pulses (glitches).
Reset output timing is shown in Figure 1.
Manual Reset Operation
The RESET pin can operate as reset output and manual
reset input. The input is edge triggered; that is, the
RESET input will initiate a reset timeout after detecting
a high to low transition.
When RESET I/O is driven to the active state, the 200
msec timer will begin to time the reset interval. If external
reset is shorter than 200 ms, Reset outputs will remain
active at least 200 ms.
Glitches shorter than 100 ns on RESET input will not
generate a reset pulse.
Hardware Data Protection
The CAT1640/41 family has been designed to solve
many of the data corruption issues that have long been
associated with serial EEPROMs. Data corruption occurs
when incorrect data is stored in a memory location which
is assumed to hold correct data.
Whenever the device is in a Reset condition, the embedded
EEPROM is disabled for all operations, including write
operations. If the Reset output is active, in progress
communications to the EEPROM are aborted and no new
communications are allowed. In this condition an internal
write cycle to the memory can not be started, but an in
progress internal non-volatile memory write cycle can not
be aborted. An internal write cycle initiated before the
Reset condition can be successfully finished if there is
enough time (5ms) before VCC reaches the minimum
value of 2V.
Figure 1. RESET/RESET Output Timing
VTH
VRVALID
VCC
tPURST
t
GLITCH
t RPD
RESET
tPURST
t RPD
RESET
Doc. No. MD-3012, Rev. D
6
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice.

6 Page









CAT1640 pdf, datenblatt
CAT1640, CAT1641
Immediate/Current Address Read
The CAT1640 and CAT1641 address counter contains
the address of the last byte accessed, incremented by
one. In other words, if the last READ or WRITE access
was to address N, the READ immediately following
would access data from address N+1. For all devices,
N=E=8,192. The counter will wrap around to Zero and
continue to clock out valid data. After the CAT1640 and
CAT1641 receives its slave address information (with
the R/W bit set to one), it issues an acknowledge, then
transmits the 8-bit byte requested. The master device
does not send an acknowledge, but will generate a
STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
dummywrite operation by sending the START condition,
slave address and byte addresses of the location it
wishes to read. After the CAT1640 and CAT1641
acknowledges, the Master device sends the START
condition and the slave address again, this time with the
R/W bit set to one. The CAT1640 and CAT1641 then
responds with its acknowledge and sends the 8-bit byte
requested. The master device does not send an
acknowledge but will generate a STOP condition.
www.DataSheet4U.com
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1640 and CAT1641 sends the
inital 8-bit byte requested, the Master will responds with
an acknowledge which tells the device it requires more
data. The CAT1640 and CAT1641 will continue to output
an 8-bit byte for each acknowledge, thus sending the
STOP condition.
The data being transmitted from the CAT1640 and
CAT1641 is sent sequentially with the data from address
N followed by data from address N+1. The READ
operation address counter increments all of the CAT1640
and CAT1641 address bits so that the entire memory
array can be read during one operation.
Figure 11. Selective Read Timing
BUS ACTIVITY:
MASTER
S
T
A
R
T
SDA LINE S
SLAVE
ADDRESS
BYTE ADDRESS
A15A8
A7A0
***
A
C
K
A
C
K
*=Dont Care Bit
S
T
A SLAVE
R ADDRESS
T
S
A
C
K
A
C
K
DATA
S
T
O
P
P
N
O
A
C
K
Figure 12. Sequential Read Timing
BUS ACTIVITY: SLAVE
MASTER ADDRESS
DATA n
SDA LINE
A
C
K
DATA n+1
DATA n+2
A AA
C CC
K KK
DATA n+x
S
T
O
P
P
N
O
A
C
K
Doc. No. MD-3012, Rev. D
12
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice.

12 Page





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