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PDF AD74111 Data sheet ( Hoja de datos )
| Número de pieza | AD74111 | |
| Descripción | Low Power Mono Audio Codec | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Low Cost, Low Powerwww.DataSheet4U.com
Mono Audio Codec
AD74111
FEATURES
2.5 V Mono Audio Codec with 3.3 V Tolerant
Digital Interface
Supports 8 kHz to 48 kHz Sample Rates
Supports 16-/20-/24-Bit Word Lengths
Multibit ⌺-⌬ Modulators with
“Perfect Differential Linearity Restoration” for
Reduced Idle Tones and Noise Floor
Data Directed Scrambling DAC – Least Sensitive to Jitter
Performance (20 Hz to 20 kHz)
85 dB ADC Dynamic Range
93 dB DAC Dynamic Range
Programmable ADC Gain
On-Chip Volume Control for DAC Channel
Software Controllable Clickless Mute
Supports 256 ؋ fS, 512 ؋ fS, and 768 ؋ fS Master Mode
Clocks
Master Clock Prescaler for Use with DSP Master Clocks
On-Chip Reference
16-Lead TSSOP Package
APPLICATIONS
Digital Video Camcorders (DVC)
Portable Audio Devices (Walkman®, PDAs, and so on)
Audio Processing
Voice Processing
Telematic Systems
General-Purpose Analog I/O
GENERAL DESCRIPTION
The AD74111 is a front-end processor for general-purpose audio
and voice applications. It features a multibit ⌺-⌬ A/D conversion
channel and a multibit ⌺-⌬ D/A conversion channel. The ADC
channel provides >67 dB THD+N and the DAC channel pro-
vides >88 dB THD+N, both over an audio signal bandwidth.
The AD74111 is particularly suitable for a variety of applications
where mono input and output channels are required, including
audio sections of digital video camcorders, portable personal
audio devices, and telematic applications. Its high quality
performance also makes it suitable for speech and telephony
applications such as speech recognition and synthesis, and modern
feature phones.
An on-chip reference voltage is included but can be powered
down and bypassed by an external reference source if required.
The AD74111 offers sampling rates that, depending on MCLK
selection and MCLK divider ratio, range from 8 kHz in the
voiceband range to 48 kHz in the audio range.
The AD74111 is available in a 16-lead TSSOP package option
and is specified for the automotive temperature range of –40°C
to +105°C.
RESET
FUNCTIONAL BLOCK DIAGRAM
MCLK DVDD1 DVDD2 AVDD
DIN
DOUT
DFS
DCLK
SERIAL
DATA
PORT
DIGITAL
FILTER
ADC
⌺-⌬
MODULATOR
GAIN
STAGE
CAPP
VIN
CAPN
REFERENCE
DIGITAL
FILTER
DAC CHANNEL
VOLUME
CONTROL
⌺-⌬ DAC
MODULATOR
VOUT
REFCAP
DGND
AGND
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
AD74111www.DataSheet4U.com
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
AVDD, DVDD2 to AGND, DGND . . . . . . . –0.3 V to +3.0 V
DVDD1 to AGND, DGND . . . . . . . . . . . . . –0.3 V to +4.5 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . . –0.3 V to DVDD1 + 0.3 V
Operating Temperature Range
Automotive (Y Version) . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
16-Lead TSSOP, θJA Thermal Impedance . . . . . . . . 150.4°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
TEMPERATURE RANGE
Parameter
Min Max
Specifications Guaranteed
Storage
–40
–65
+105
+150
Unit
ºC
ºC
Model
AD74111YRU
ORDERING GUIDE
Range
–40ºC to +105ºC
Package
RU-16
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD74111 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0
–5–
5 Page 
DFS
DCLK
DIN
DOUT
tFS
tFH
tFD
tCH
tCL
MSB
MSB
MSB–1
MSB–1
MSB–2
tDS
tDH
MSB–2
tDD
Figure 11. Serial Port (SPORT) Timing
AD74111www.DataSheet4U.com
Serial Port Operating Modes
The serial port of the AD74111 can be programmed to operate
in a variety of modes depending on the requirements and flex-
ibility of the DSP to which it is connected. The two principal
modes of operation are Mixed mode and Data mode.
Mixed Mode
Mixed mode allows the control registers of the AD74111 to be
programmed and read back. It also allows data to be sent to the
DACs and data to be read from the ADCs. In Mixed mode,
there are separate data slots, each with its own frame synchroni-
zation signal (DFS) for control and DAC or ADC information.
The AD74111 powers up in Mixed mode by default to allow
the control registers to be programmed. Figure 13 shows the
default setting for Mixed mode.
Data Mode
Data mode can be used when programming or reading the
control registers is no longer required. Data mode provides a
frame synchronization (DFS) pulse for each sample of data.
Once the part has been programmed into Data mode, the only
way to change the control registers is to perform a hardware reset
to put the AD74111 back into Mixed mode. Figure 15 shows
the default setting for Data mode.
Data-Word Length
The AD74111 can be programmed to send DAC audio data
and receive ADC audio data in different word length formats of
16, 20, or 24 bits. The default mode is 16 bits, but this can be
changed by programming Control Register C for the appropriate
word length.
Selecting Master or Slave Mode
The initial operating mode of the AD74111 is determined by
the state of the DIN pin following a reset. If the DIN pin is high
during this time, Slave mode is selected. In Slave mode, the
DFS and DCLK pins are inputs and the control signals for
these pins must be provided by the DSP or other controller. If
the DIN pin is low immediately following a reset, the AD74111
will operate in Master mode.
Master Mode Operation
In Master mode, the DFS and DCLK pins are outputs from the
AD74111. This is the easiest mode in which to use the AD74111
because the correct timing relationship between sample rate,
DCLK, and DFS is controlled by the AD74111.
Slave Mode Operation
In Slave mode, the DFS and DCLK pins are inputs to the
AD74111. Care needs to be exercised when designing a system
to operate the AD74111 in this mode as the relationship between
the sample rate, DCLK, and DFS needs to be controlled by the
DSP or other controller and must be compatible with the inter-
nal DAC/ADC engine of the AD74111. Figure 12 shows a block
diagram of the DAC engine and the AD74111’s serial port. The
sample rate for the DAC engine is determined by the MCLK
and MCLK prescalers. The DAC engine will read data from the
DAC Data register at this rate. It is therefore important that the
serial port is updated at the same rate, as any error between the
two will accumulate and eventually cause the DAC engine to have
to resynchronize with the serial port, which will cause erroneous
values on the DAC output pins.
RESYNC*
LOAD DAT
DAC ENGINE
VOUT
DAC DATA REGISTER
DFS
DIN
SERIAL PORT
*RESYNC IS ONLY USED WHEN THE DAC BECOMES
UNSYNCHRONIZED WITH THE SERIAL PORT
Figure 12. DAC Engine
In most cases, it is easy to keep a DSP in synchronization with
the AD74111 if they are both run from the same clock or the
DSP clock is a multiple of the AD74111’s MCLK. In this case,
REV. 0
–11–
11 Page | ||
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| PDF Descargar | [ Datasheet AD74111.PDF ] | |
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