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PDF CAT34C02 Data sheet ( Hoja de datos )
| Número de pieza | CAT34C02 | |
| Descripción | 2 kb I2C EEPROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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CAT34C02
2-Kb I2C EEPROM for DDR2 DIMM Serial Presence Detect
www.DataSheet4U.com
FEATURES
■ Supports Standard and Fast I2C Protocol
■ 1.7 V to 5.5 V Supply Voltage Range
■ 16-Byte Page Write Buffer
■ Hardware Write Protection for entire memory
■ Software Write Protection for lower 128 Bytes
■ Schmitt Triggers and Noise Suppression Filters
on I2C Bus Inputs (SCL and SDA).
■ Low power CMOS technology
■ 1,000,000 program/erase cycles
■ 100 year data retention
■ RoHS compliant “
”&“
8-pin TSSOP and TDFN packages
”
■ Industrial temperature range
PIN CONFIGURATION
TSSOP (Y)
TDFN (VP2)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
For the location of Pin 1, please consult the
corresponding package drawing.
PIN FUNCTIONS
A0, A1, A2
SDA
SCL
WP
VCC
VSS
Device Address
Serial Data
Serial Clock
Write Protect
Power Supply
Ground
DEVICE DESCRIPTION
The CAT34C02 is a 2-Kb Serial CMOS EEPROM,
internally organized as 16 pages of 16 bytes each, for
a total of 256 bytes of 8 bits each.
It features a 16-byte page write buffer and supports
both the Standard (100 kHz) as well as Fast (400 kHz)
I2C protocol.
Write operations can be inhibited by taking the WP pin
High (this protects the entire memory) or by setting an
internal Write Protect flag via Software command (this
protects the lower half of the memory).
In addition to Permanent Software Write Protection,
the CAT34C02 also features JEDEC compatible
Reversible Software Write Protection for DDR2 Serial
Presence Detect (SPD) applications operating over
the 1.7 V to 3.6 V supply voltage range.
The CAT34C02 is fully backwards compatible with
earlier DDR1 SPD applications operating over the
1.7 V to 5.5 V supply voltage range.
FUNCTIONAL SYMBOL
VCC
SCL
A2, A1, A0
WP
CAT34C02
SDA
VSS
* Catalyst carries the I2C protocol under a license from the Philips Corporation.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1095, Rev. C
1 page  
Figure 1. Start/Stop Timing
CAT34C02
www.DataSheet4U.com
SDA
SCL
START BIT
Figure 2. Slave Address Bits
STOP BIT
1 0 1 0 A2 A1 A0 R/W
DEVICE ADDRESS
Figure 3. Acknowledge Timing
SCL FROM
MASTER
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
1
89
ACKNOWLEDGE
Figure 4. Bus Timing
tF
SCL
tSU:STA
SDA IN
SDA OUT
tLOW
tHIGH
tLOW
tR
tHD:DAT
tHD:STA
tSU:DAT
tAA tDH
tSU:STO
tBUF
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc No. 1095, Rev. C
5 Page 
Table 1. SWP Commands
CAT34C02
www.DataSheet4U.com
Control Pin Levels (1)
Action
WP A2 A1 A0
Flag State (2)
Slave Address
ACK Address ACK Data ACK Write
PSWP RSWP b7 to b4 b3 b2 b1 b0 ?
Byte ? Byte ? Cycle
X A2 A1 A0
1
X
A2 A1 A0 X No
Set GND A2 A1 A0
PSWP VCC A2 A1 A0
0
0
X
X
A2 A1 A0
A2 A1 A0
0
0
Yes
Yes
X Yes X Yes Yes
X Yes X No No
X A2 A1 A0
X GND GND VHV
0
1
X
X
A2 A1 A0 1
001X
Yes
No
Set
RSWP
X
GND
VCC
GND
GND
GND
GND
GND
GND
VHV
VHV
VHV
0
0
0
1 0 0 1 X No
0 0110 0 0 1 0 Yes
0 0 0 1 0 Yes
X Yes X Yes Yes
X Yes X No No
X GND GND VHV
X GND VCC VHV
0
1
0
X
0 0 1 1 Yes
0 1 1 X No
Clear GND GND VCC
RSWP VCC GND VCC
VHV
VHV
0
0
X
X
0 1 1 0 Yes
0 1 1 0 Yes
X Yes X Yes Yes
X Yes X No No
X GND VCC VHV
0
X
0 1 1 1 Yes
Note:
(1) Here A2, A1 and A0 are either at VCC or GND.
(2) 1 stands for ‘Set’, 0 stands for ‘Not Set’, X stands for ‘don’t care’.
Figure 12. Software Write Protect (Write)
BUS ACTIVITY:
MASTER
S
T
A
R
T
SDA LINE S
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
S
T
O
P
XXXXXXXX XXXXXXXX P
AA
CC
KK
X = Don't Care
AN
C or O
K
A
C
K
Figure 13. Software Write Protect (Read)
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
S
SLAVE
ADDRESS
S
T
O
P
P
AN
C or O
K
A
C
K
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc No. 1095, Rev. C
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet CAT34C02.PDF ] | |
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