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PDF CAT24AC128 Data sheet ( Hoja de datos )
| Número de pieza | CAT24AC128 | |
| Descripción | 128kbit I2C Serial CMOS EEPROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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Not Recommended for New Design,
Replace with CAT24C128
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CAT24AC128
ALOGEN FR
128kbit I2C Serial CMOS EEPROM With Three Chip Address Input Pins
FEATURES
LEA D F REETM
I 400kHz (2.5V) and 100kHz (1.8V) I2C bus
compatibility
I 1.8 to 5.5 volt operation
I Low power CMOS technology
I Schmitt trigger filtered inputs for noise
suppression
I 64-Byte page write buffer
I Self-timed write cycle with auto-clear
I Commercial, industrial and extended
automotive temperature ranges
I Write protect feature
– Entire array protected when WP at VIH
I 1,000,000 program/erase cycles
I 100 year data retention
I 8-Pin DIP, 8-Pin SOIC (JEDEC/EIAJ) or
14-pin TSSOP
DESCRIPTION
The CAT24AC128 is a 128kbit Serial CMOS EEPROM
internally organized as 16,384 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The CAT24AC128
features a 64-byte page write buffer. The device operates
via the I2C bus serial interface and is available in 8-pin
DIP, 8-pin SOIC or 14-pin TSSOP packages. Three
device address inputs allows up to 8 devices to share a
common 2-wire I2C bus.
PIN CONFIGURATION
DIP Package (P, L) SOIC Package (J, K, W, X)
A0
A1
A2
VSS
1
2
3
4
8 VCC A0 1
7 WP
A1 2
6 SCL
A2 3
5 SDA VSS 4
8 VCC
7 WP
6 SCL
5 SDA
TSSOP Package (U14, Y14)
A0
A1
NC
NC
NC
A2
VSS
1
2
3
4
5
6
7
14 V CC
13 WP
12 NC
11 NC
10 NC
9 SCL
8 SDA
BLOCK DIAGRAM
EXTERNAL LOAD
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SDA
START/STOP
LOGIC
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
512
XDEC 256
E2PROM
256X512
CONTROL
WP LOGIC
PIN FUNCTIONS
Pin Name
Function
SDA
Serial Data/Address
SCL Serial Clock
WP Write Protect
VCC +1.8V to +5.5V Power Supply
VSS Ground
A0 - A2
Device Address Inputs
SCL
STATE COUNTERS
A0 SLAVE
A1 ADDRESS
A2 COMPARATORS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1028, Rev. J
1 page  
Not Recommended for New Design,
Replace with CAT24C128
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 (Fig. 5). The next three significant bits (A2, A1, A0)
are the device address bits and define which device the
master is accessing. Up to eight CAT24AC128 devices
may be individually addressed by the system. The last
bit of the slave address specifies whether a Read or
Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24AC128 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24AC128 then performs a Read or Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
The CAT24AC128 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
Figure 4. Acknowledge Timing
CAT24AC128
www.DataSheet4U.com
When the CAT24AC128 begins a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT24AC128 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
address pointers of the CAT24AC128. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memory location. The CAT24AC128 acknowledges once
more and the Master generates the STOP condition. At
this time, the device begins an internal programming
cycle to nonvolatile memory. While the cycle is in
progress, the device will not respond to any request from
the Master device.
Page Write
The CAT24AC128 writes up to 64 bytes of data, in a
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
SCL FROM
MASTER
1
89
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1 0 1 0 A2 A1 A0 R/W
*A0, A1 and A2 must compare to its corresonding hard wired inputs (pins 1, 2 and 3).
5 Doc. No. 1028, Rev. J
5 Page 
Not Recommended for New Design,
Replace with CAT24C128
REVISION HISTORY
Date
07/7/2004
Rev.
G
07/27/2004
06/23/2005
H
I
01/16/2006
J
Reason
Added Die Revision to Ordering Information
Started revision history
Updated DC Operating Characteristics table and notes
Update Features
Update Pin Functions
Update Reliability Characteristics
Update D.C. Operating Characteristics
Update A.C. Characteristics
Update Read Operations
Update Figures 8, 9, 10
Add Figure 11
Update Ordering Information
Update Ordering Information
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Copyrights, Trademarks and Patents
© Catalyst Semiconductor, Inc.
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
Beyond Memory ™, DPP ™, EZDim ™, LDD ™, MiniPot™ and Quad-Mode™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Publication #: 1028
Revison:
J
Issue date: 01/16/06
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet CAT24AC128.PDF ] | |
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